The Week In Review: Manufacturing

By Mark LaPedus - 27 Oct, 2017 - Comments: 0

Chipmakers At this week’s International Wafer-Level Packaging Conference (IWLPC), Samsung disclosed details about its efforts in the panel-level fan-out market. Samsung as well as ASE, Nepes and others are developing a next-generation fan-out technology using a panel-level format. In panel-level fan-out packaging, you can put more die on a panel as compared to a traditional round wafer, w... » read more

The Week In Review: Design/IoT

By Jesse Allen - 03 Apr, 2015 - Comments: 0

IP Synopsys unveiled a line of vision processor IP cores optimized for high-performance embedded vision applications. The processors can be used with any host processors, sport multiple cores and implement a convolutional neural network to deliver more than 1000 GOPS/W, plus a software programming environment that supports OpenVX and OpenCV libraries. Deals Andes Technology and eMemory Tec... » read more

The Power Of 3D

By Cheryl Ajluni - 14 Jan, 2010 - Comments: 0

By Cheryl Ajluni Much to the dismay of anyone who recently splurged on a new Blu-ray disk player or flat-panel HDTV, 3D stereoscopic content has become the talk of the town or, in this case, the 2010 Consumer Electronics Show. Sure, we’ve been down this road before. After all, 3D is nothing new. But it now appears ready to explode into the home in the form of 3D television (Figure 1). Bol... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: AppliedMicro

The Week In Review: Manufacturing

The Week In Review: Design/IoT

The Power Of 3D