New End Markets, More Demand For Complex Chips


Experts at the Table: Semiconductor Engineering sat down to discuss economic conditions and how that affects chip design with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front... » read more

Week In Review: Design, Low Power


Tools & IP MIPS announced its first products based on the RISC-V ISA. The eVocore IP cores are designed to provide a flexible foundation for heterogeneous compute, supporting combinations of eVocore processors as well as other accelerators, with a Coherence Manager that maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices. They target high-performan... » read more

New Robots Require New Ways To Think About Processors


We’re on the cusp of a revolution in robots. After years of relatively moderate growth, sales of commercial and industrial robots are slated to grow by 25% to 35% per year over the next decade, according to Boston Consulting Group, and could reach $260 billion by 2030 to meet the demands of manufacturers, retailers and others to streamline supply chains, enhance safety and boost productivity.... » read more

Software-Defined Cars


Automotive architectures are becoming increasingly software-driven, a shift that simplifies upgrades and makes it easier to add new features into vehicles. All of this is enabled by the increasing digitalization of automotive functions and features, shifting from mechanical to electrical design, and increasingly from analog to digital data. That enables OEMs to add or up-sell features years ... » read more

Every Walk’s A Hit: Making Page Walks Single-Access Cache Hits


As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically "flattening" the page table: merging two levels of traditional 4 KB p... » read more

Blog Review: May 11


Ansys' Vidyu Challa checks out how to identify the most important battery metrics for a particular application and trade these off against others with a focus on the important considerations when selecting the right battery for a consumer application, such as rechargeability, energy density, power density, shelf life, safety, form factor, cost, and flexibility. Cadence's Shyam Sharma points ... » read more

Hidden Impacts Of Software Updates


Over-the-air updates can reduce obsolescence over longer chip and system lifetimes, but those updates also can impact reliability, performance, and affect how various resources such as memory and various processing elements are used. The connected world is very familiar with over-the-air (OTA) updates in smart phones and computers, where the software stack — firmware, operating systems, dr... » read more

Lots Of Data, But Uncertainty About What To Do With It


Experts at the Table: Semiconductor Engineering sat down to talk about silicon lifecycle management in heterogeneous designs, where sensors produce a flood of data, with Prashant Goteti, principal engineer at Intel; Rob Aitken, R&D fellow at Arm; Zoe Conroy, principal hardware engineer at Cisco; Subhasish Mitra, professor of electrical engineering and computer science at Stanford University... » read more

Building Security Into ICs From The Ground Up


Cyberattacks are becoming more frequent and more sophisticated, but they also are starting to compromise platforms that until recently were considered unbreakable. Consider blockchains, for example, which were developed as secure, distributed ledger platforms. All of them must be updated with the same data for a transaction to proceed. But earlier this year a blockchain bridge platform calle... » read more

Blog Review: May 4


In a podcast, Arm's Geof Wheelwright chats with Steve Furber of the University of Manchester and Christian Mayr of Technische Universität Dresden about spiking neural networks and the SpiNNaker project to build a platform for realistic real-time models of brain functions. Synopsys' Licinio Sousa checks out how the MIPI protocol enables the connectivity needed for sensor fusion and increasin... » read more

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