tag: ARM

Which Chip Interconnect Protocol Is Better?
By Ed Sperling - 11 May, 2020 - Comments: 0

Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversation... » read more

Blog Review: May 6
By Jesse Allen - 06 May, 2020 - Comments: 0

In a blog for Arm, Javier Fernandez-Marques of Oxford University digs into how to make the best use of quantized neural network models and why it's so important to consider what algorithms will be running when deciding which model architecture to implement, and which quantization strategy to adopt for the model. Synopsys' Taylor Armerding explains why, with a largely remote workforce, it may... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 01 May, 2020 - Comments: 0

Data center, 5G security Nvidia won approval for its Mellanox Technologies Ltd. deal from China, according to an article on Bloomberg. Mellanox chips split up and manage AI datasets for parallel processing, which can be used in data centers for computing. Rambus has released security for 800 Gigbit Ethernet MAC (media access control) for enhanced data center and 5G infrastructure. It secure... » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 May, 2020 - Comments: 0

Nvidia completed its $7 billion acquisition of Mellanox. The acquisition, initially announced over a year ago, brings Mellanox’s high-performance networking and interconnect technology to Nvidia's server efforts and gives the company full end-to-end offerings in the data center space. To date, this is the largest acquisition in Nvidia's history. Tools & IP Synopsys debuted its 3DIC Co... » read more

Blog Review: April 29
By Jesse Allen - 29 Apr, 2020 - Comments: 0

Arm's Paul Whatmough checks out SCALE-Sim, an open source cycle-accurate simulator specifically for neural processing unit (NPU) architectures. Mentor's Neil Johnson shows how a complete verification methodology requires complementary deployment of multiple techniques, with different options at each level of abstraction. Cadence's Paul McLellan checks out challenges in automotive reliabil... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 24 Apr, 2020 - Comments: 0

PCs get work-from-home bump Rather than using Intel chips, Apple will be making its own chips for its Mac computers, using Arm cores, Bloomberg reports. TSMC will manufacture the chips. Intel, meanwhile, was up 14% quarter year-over-year its PC business, which it attributes to more people working from home and needed new equipment. Despite a strong quarter, however, the company pulled its 2... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 Apr, 2020 - Comments: 0

Tools & IP Codasip unveiled its Codasip SweRV Core EH1 Support Package, which provides support for Western Digital's open source RISC-V-based core. The support package provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based SoC with support for leading EDA open and commercial flows. A free basic version is available ... » read more

Practical Processor Verification
By Brian Bailey - 23 Apr, 2020 - Comments: 0

Custom processors are making a resurgence, spurred on by the early success of the RISC-V ISA and the ecosystem that is rapidly building around it. But this shift is amid questions about whether processor verification has become a lost art. Years ago custom processors were common. But as the market consolidated around a handful of companies, so did the tools and expertise needed to develop th... » read more

Using Processor Trace At The System Level
By Ann Mutschler - 23 Apr, 2020 - Comments: 0

The race to process more data faster using less power is creating a series of debug challenges at the system level, where developers need to be able to trace interactions across multiple and often heterogeneous processing elements that may function independently of each other. In general, trace is a hardware debug feature that allows the run-time behavior of IP to be monitored. More specific... » read more

Re-Imagining The GPU
By SE Staff - 23 Apr, 2020 - Comments: 0

John Rayfield, CTO at Imagination Technologies, sat down with Semiconductor Engineering to talk about RISC-V, AI, and computing architectures. What follows are excerpts of that conversation. SE: What your plans are for RISC-V? Rayfield: We're actively finalizing the integration of RISC-V cores into future-generation GPUs. That work has been going on for several months. Moving forward, we'... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy