tag: Arteris IP

Power Optimization: What’s Next?
By Brian Bailey - 17 May, 2021 - Comments: 2

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

HBM Takes On A Much Bigger Role
By Brian Bailey - 13 May, 2021 - Comments: 1

High-bandwidth memory is getting faster and showing up in more designs, but this stacked DRAM technology may play a much bigger role as a gateway for both chiplet-based SoCs and true 3D designs. HBM increasingly is being viewed as a way of pushing heterogenous distributed processing to a completely different level. Once viewed as an expensive technology that only could be utilized in the hig... » read more

NoCs In Authoritative MPSoC Reference
By Kurt Shuler - 06 May, 2021 - Comments: 0

The MPSoC Forum, sponsored by IEEE and other industry associations, hosts an annual conference in beautiful places around the planet. It is dedicated to showcasing renowned academic and industry experts in multicore and multiprocessor architectures. The goal is to explore trends in system-on-chip (SoC) hardware and software architectures and applications. An additional purpose is to consider th... » read more

IC Security Threat Grows As More Devices Are Connected
By Ann Mutschler - 06 May, 2021 - Comments: 0

Designing for security is beginning to gain traction across a wider swath of chips and systems as more of them are connected to the Internet and to each other, sometimes in safety- and mission-critical markets where the impact of a cyber attack can be devastating. But it's also becoming more difficult to design security into these systems. Unlike in the past, connectivity is now considered e... » read more

Steep Spike For Chip Complexity And Unknowns
By Ed Sperling - 05 May, 2021 - Comments: 0

Cramming more and different kinds of processors and memories onto a die or into a package is causing the number of unknowns and the complexity of those designs to skyrocket. There are good reasons for combining all of these different devices into an SoC or advanced package. They increase functionality and can offer big improvements in performance and power that are no longer available just b... » read more

Security Concerns Rise For Connected Autos
By John Koon - 29 Apr, 2021 - Comments: 0

The auto industry is transforming itself toward a future in which the automobile increasingly will be connected using V2X and 5G. Driver assistance will improve, and ultimately cars will be guided by AI and machine learning. But all of this will be closely watched by hackers, looking for an opening and a potentially large and untraceable payout. The replacement of mechanical functionality wi... » read more

Many Chiplet Challenges Ahead
By Brian Bailey - 12 Apr, 2021 - Comments: 0

Over the past couple of months, Semiconductor Engineering has looked into several aspects of 2.5D and 3D system design, the emerging standards and steps that the industry is taking to make this more broadly adopted. This final article focuses on the potential problems and what remains to be addressed before the technology becomes sustainable to the mass market. Advanced packaging is seen as ... » read more

Interconnects In A Domain-Specific World
By Brian Bailey - 08 Apr, 2021 - Comments: 0

Moving data around is probably the least interesting aspect of system design, but it is one of three legs that defines the key performance indicators (KPI) for a system. Computation, memory, and interconnect all need to be balanced. Otherwise, resources are wasted and performance is lost. The problem is that the interconnect is rarely seen as a contributor to system functionality. It is seen... » read more

More Data Drives Focus On IC Energy Efficiency
By Ann Mutschler - 08 Apr, 2021 - Comments: 0

Computing workloads are becoming increasingly interdependent, raising the complexity level for chip architects as they work out exactly where that computing should be done and how to optimize it for shrinking energy margins. At a fundamental level, there is now more data to compute and more urgency in getting results. This situation has forced a rethinking of how much data should be moved, w... » read more

SoC Integration Complexity: Size Doesn’t (Always) Matter
By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

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