Week In Review: Design, Low Power

By Jesse Allen - 22 May, 2020 - Comments: 0

Tools & IP Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIP... » read more

Choosing Between CCIX And CXL

By Ed Sperling - 19 May, 2020 - Comments: 0

Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversati... » read more

Spiking Neural Networks: Research Projects or Commercial Products?

By Bryon Moyer - 18 May, 2020 - Comments: 2

Spiking neural networks (SNNs) often are touted as a way to get close to the power efficiency of the brain, but there is widespread confusion about what exactly that means. In fact, there is disagreement about how the brain actually works. Some SNN implementations are less brain-like than others. Depending on whom you talk to, SNNs are either a long way away or close to commercialization. Th... » read more

Week In Review: Design, Low Power

By Jesse Allen - 15 May, 2020 - Comments: 0

Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 15 May, 2020 - Comments: 0

Security Ninety-one percent of commercial applications contain outdated or abandoned open-source components —a security threat, says Synopsys in its recently released report 2020 Open Source Security and Risk Analysis (OSSRA). In the fifth annual edition of the report, Synopsys’ research team in its Cybersecurity Research Center (CyRC) found that 99% of the 1,250 commercial codebases revie... » read more

Which Chip Interconnect Protocol Is Better?

By Ed Sperling - 11 May, 2020 - Comments: 0

Inference Moves To The Network

By Bryon Moyer - 07 May, 2020 - Comments: 0

Machine-learning inference started out as a data-center activity, but tremendous effort is being put into inference at the edge. At this point, the “edge” is not a well-defined concept, and future inference capabilities will reside not only at the extremes of the data center and a data-gathering device, but at multiple points in between. “Inference isn't a function that has to resid... » read more

Vehicle Communications Network Is Due For Overhaul

By Ann Mutschler - 07 May, 2020 - Comments: 1

The Controller Area Network (CAN), one of the main communications networks in an automobile, is headed for a security overhaul — if not a wholesale replacement. Initially devised in the 1980s to allow electronic components in a vehicle to communicate directly without a central computer in between, the CAN bus has become a growing security risk as more functions are automated and integrated... » read more

Key Drivers In New Chip Industry Outlook

By Ed Sperling - 04 May, 2020 - Comments: 0

How well the semiconductor industry fares over the next 12 to 24 months depends upon the evolution of a virus. That alone will determine the correct model for an economic rebound — V, U, extended U, or maybe even a double U. But what's also becoming clear is those models don't apply uniformly to all sectors or sub-sectors of the semiconductor industry. Looked at as a whole, the entire indu... » read more

Last-Level Cache

By Ed Sperling - 06 Apr, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

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Knowledge Centers
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tag: Arteris IP

Week In Review: Design, Low Power

Choosing Between CCIX And CXL

Spiking Neural Networks: Research Projects or Commercial Products?

Week In Review: Design, Low Power

Week In Review: Auto, Security, Pervasive Computing

Which Chip Interconnect Protocol Is Better?

Inference Moves To The Network

Vehicle Communications Network Is Due For Overhaul

Key Drivers In New Chip Industry Outlook

Last-Level Cache