Executive Insight: K. Charles Janac

By Ed Sperling - 24 May, 2016 - Comments: 0

K. Charles Janac, chairman and CEO of Arteris, sat down with Semiconductor Engineering to talk about what's changing in the automotive market, the impact of big data, and heterogeneous cache coherency. What follows are excerpts of that discussion. SE: What are the big changes you're seeing in semiconductor design? Janac: There are a lot of changes right now. Mobility is slowing down and b... » read more

The Week In Review: Design

By Jesse Allen - 20 May, 2016 - Comments: 1

Acquisitions ARM acquired embedded computer vision and imaging technology company [getentity id="22917" comment="Apical"] for $350 million in cash. According to ARM, the company's technology has been utilized in more than 1.5 billion smartphones and in about 300 million other consumer and industrial devices. Synopsys acquired [getentity id="22916" comment="Simpleware"], a provider of soft... » read more

Power-Centric Chip Architectures

By Ed Sperling - 12 May, 2016 - Comments: 0

As traditional scaling runs out of steam, new chip architectures are emerging with power as the starting point. While this trend has been unfolding for some time, it is getting an extra boost and sense of urgency as design teams weigh a growing number of design challenges and options across a variety of new markets. Among the options are [getkc id="196" kc_name="multi-patterning"] and [getkc... » read more

Rethinking Processor Architectures

By Ed Sperling - 05 May, 2016 - Comments: 2

The semiconductor industry's obsession with clock speeds, cores and how many transistors fit on a piece of silicon may be nearing an end for real this time. The [getentity id="22048" comment="IEEE"] said it will develop the International Roadmap for Devices and Systems (IRDS), effectively setting the industry agenda for future silicon benchmarking and adding metrics that are relevant to specifi... » read more

End Of Mixed Signal Engineering?

By Ed Sperling - 04 May, 2016 - Comments: 1

EDA companies are stepping back after years of trying to force engineers to combine analog and digital disciplines. Rather than emphasizing [getkc id="38" kc_name="mixed signal"] as a single expertise, they are building bridges and translation mechanisms between the two worlds. The moves cap more than a decade of trying to find optimal ways to pack [getkc id="37" kc_name="analog"] and digita... » read more

The Week In Review: Design/IoT

By Jesse Allen - 29 Apr, 2016 - Comments: 0

IP & Chips Synopsys debuted MIPI I3CSM controller IP, which incorporates in-band interrupts within the 2-wire interface to deliver low pin count. The IP supports all data rates up to 26.7 Mbps, dynamic address allocation, multi-master operations and 32-bit ARM AMBA Advanced Peripheral Bus slave interface. Marvell unveiled a family of Ethernet transceivers fully optimized for 2.5Gbps a... » read more

Way Too Much Data

By Ed Sperling - 28 Apr, 2016 - Comments: 0

Moving to the next process nodes will produce volumes more data, forcing chipmakers to adopt more expensive hardware to process and utilize that data, more end-to-end methodologies, as well as using tools and approaches that in the past were frequently considered optional. Moreover, where that data needs to be dealt with is changing as companies adopt a "shift left" approach to developing so... » read more

Bridging Hardware And Software

By Ann Mutschler - 28 Apr, 2016 - Comments: 1

The barriers between hardware and software design and verification are breaking down with more intricately integrated systems, bringing together different disciplines and tools. But there are lingering questions about exactly what this shift means design methodologies, team interactions, and what kind of training will be required in the future. Playing heavily into this is the fact that toda... » read more

The Week In Review: Design/IoT

By Jesse Allen - 22 Apr, 2016 - Comments: 0

Tools Rambus released the latest version of its platform for analysis of power and electromagnetic side-channel attacks, featuring upgrades to the workstation software and user interface for enhanced system performance and usability in ASIC and FPGA side-channel vulnerability testing. Deals Istuary Innovation Group licensed Arteris' FlexNoC interconnect IP for enterprise storage contro... » read more

The Week In Review: Design/IoT

By Jesse Allen - 01 Apr, 2016 - Comments: 0

Tools Synopsys unveiled a new custom design solution targeting FinFET layout, introducing visually-assisted routing automation, a built-in design rule checking engine, templates to apply previous layout decisions to new designs, and IC Compiler integration. TSMC certified the new tool for 10nm and 7nm FinFET process technologies. It has also been adopted by STMicroelectronics, GSI Technology... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Arteris

Executive Insight: K. Charles Janac

The Week In Review: Design

Power-Centric Chip Architectures

Rethinking Processor Architectures

End Of Mixed Signal Engineering?

The Week In Review: Design/IoT

Way Too Much Data

Bridging Hardware And Software

The Week In Review: Design/IoT

The Week In Review: Design/IoT