tag: Arteris

Neural Net Computing Explodes
By Gale Morrison - 06 Oct, 2016 - Comments: 1

Neural networking with advanced parallel processing is beginning to take root in a number of markets ranging from predicting earthquakes and hurricanes to parsing MRI image datasets in order to identify and classify tumors. As this approach gets implemented in more places, it is being customized and parsed in ways that many experts never envisioned. And it is driving new research into how el... » read more

What Can Go Wrong In Automotive
By Ed Sperling - 06 Oct, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

The Week In Review: Design
By Jesse Allen - 30 Sep, 2016 - Comments: 0

Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

Building Chips That Can Learn
By Ed Sperling - 29 Sep, 2016 - Comments: 0

The idea that devices can learn optimal behavior rather than relying on more generalized hardware and software is driving a resurgence in artificial intelligence, machine leaning, and cognitive computing. But architecting, building and testing these kinds of systems will require broad changes that ultimately could impact the entire semiconductor ecosystem. Many of these changes are wel... » read more

Plugging Holes In Machine Learning
By Ed Sperling - 19 Sep, 2016 - Comments: 0

The number of companies using machine learning is accelerating, but so far there are no tools to validate, verify and debug these systems. That presents a problem for the chipmakers and systems companies that increasingly rely on machine learning to optimize their technology because, at least for now, it creates the potential for errors that are extremely difficult to trace and fix. At the s... » read more

The Week In Review: Design
By Jesse Allen - 16 Sep, 2016 - Comments: 0

IP Sonics unveiled Energy Processing Unit (EPU) IP, based on the company's ICE-Grain power architecture, to better manage and control circuit idle time. The IP facilitates design of SoC power architecture and implementation and verification of the resulting power management subsystem. Synopsys debuted ARC SEM security processors with timing and power randomization features to protect agai... » read more

The Week In Review: Design
By Jesse Allen - 09 Sep, 2016 - Comments: 0

M&A Intel will acquire Movidius, adding the company's low-power vision processing unit to its growing computer vision efforts that include a depth-sensing camera and machine learning projects. At the same time, Intel is shedding cybersecurity unit McAfee (acquired in 2011 for $7.7 billion and re-named Intel Security in 2014). Intel will retain a 49% stake in the business with the 51% rem... » read more

What’s Missing From Machine Learning
By Ed Sperling - 01 Sep, 2016 - Comments: 1

Machine learning is everywhere. It's being used to optimize complex chips, balance power and performance inside of data centers, program robots, and to keep expensive electronics updated and operating. What's less obvious, though, is there are no commercially available tools to validate, verify and debug these systems once machines evolve beyond the final specification. The expectation is th... » read more

All You Need Is Cache (Coherency) To Scale Next-Gen SoC Performance
By Kurt Shuler - 25 Aug, 2016 - Comments: 0

Life on the SoC performance front remains a withering battle sometimes, because things can seem fairly bleak. As transistor scaling becomes more expensive below 10-nanometer feature sizes, every day it becomes harder to double performance every 18-months or so and stay competitive. Nowhere is the pain of this battle more acute than in consumer and automotive systems, where low cost is the key t... » read more

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP
By Arteris - 24 Aug, 2016 - Comments: 0

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication bet... » read more

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