The Week In Review: Design

Synopsys adds to security portfolio; Mentor adds way to measure AMS defect coverage; emulation and simulation acceleration; Thread launches reference test bed.


Synopsys added to its software integrity and security business with the acquisition of services company Cigital and its 2015 spinout focused on tools, Codiscope. Cigital specializes in professional and managed services for identifying, remediating and preventing vulnerabilities in software applications. Terms of the deal were not disclosed.

Mentor Graphics rolled out a new platform for measuring defect coverage for tests involving analog of mixed-signal circuits. The company new platform can reduce the cost of test by pointing to which tests do not increase coverage. It also works with existing circuit simulators to measure opens, shorts, extreme variations and user-defined defects.

Aldec launched the latest update to its software package for emulation and simulation acceleration on HES-7 and custom, in-house high speed prototyping boards. The release includes a setup flow for Xilinx UltraScale FPGA technology and support for a new HES board which contains three XCVU440 devices on a single PCB with an estimated capacity of 79 million ASIC gates.

Cadence’s OrCAD Capture tool now includes XJTAG DFT Assistant, an interface to increase the design for test (DFT) and debug capabilities of the schematic capture and PCB design system through detection and correction of JTAG errors before the PCB is produced.

Seica, a supplier of automated test equipment, will offer the Mentor Graphics’ Valor Process Preparation tool to users of its Pilot flying probe testers.

The Thread Group released its initial hardware reference test bed and test harness and opened its test lab to members. Test bed participants ARM, NXP and Silicon Labs released the first conforming stacks that have successfully passed testing based on the Thread 1.1 technical specification.

Antonio J. Viana, former ARM executive and commercial IP industry veteran, joined Arteris’ board of directors. Viana is also chairman of the board for a Swiss/US based IP start-up company specializing in next generation noise reduction and ultra-low power, signal integrity technology.

Plus, the deadline is coming up for DAC research track submissions: abstracts need to be in by November 15th and manuscripts by the 22nd.

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