tag: Arteris

ISO 26262: Top 3 Reasons For Hardware Implementation Of Functional Safety
By Kurt Shuler - 24 Sep, 2015 - Comments: 0

I’ve written articles before about ISO 26262 Certification because many SoC design teams are challenged by the barriers they have to overcome to achieve automotive functional safety, especially if they previously enjoyed success in mobility or computing but now want to shift attention to the growing array of electronics used in transportation such as automated driver assistance systems (ADAS)... » read more

The Next Level Of Abstraction For System Design
By Frank Schirrmeister - 24 Sep, 2015 - Comments: 1

Recently there have been a lot of discussions again about the next level of design abstraction for chip design. Are we there yet? Will we ever get there? Is it SystemC? UML/SysML perhaps? I am taking the approach of simply claiming victory: Over the last 20 years we have moved up beyond RTL in various areas—just in a fragmented way. However, the human limitations on our capacity for processin... » read more

The Price Of Consolidation
By Ed Sperling - 24 Sep, 2015 - Comments: 0

Consolidation is causing far-reaching changes across the global semiconductor ecosystem due to the size of companies being bought and the dearth of startups to replenish those being acquired. Coupled with the rising cost and difficulty of shrinking features down to advanced process nodes—many argue that is the largest driver of consolidation—the market dynamics for who's buying IP, EDA t... » read more

Rethinking Differentiation
By Ed Sperling - 28 Aug, 2015 - Comments: 0

Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers. The traditional metrics of faster performance, lower power and less area/cost, which are leftovers from the PC era, no longer are a guarantee of success despite the fact that they are still baseline metrics for many designs. Even new metrics such as ecosystem completeness, w... » read more

Software Driving More Hardware Designs
By Ed Sperling - 27 Aug, 2015 - Comments: 2

The influence of software engineers is growing inside of chip and systems companies, reversing a decades-old trend of matching the software to the fastest or most power-efficient hardware and raising as-yet unanswered questions about what will change in SoC design. The shift is particularly evident in chips developed for high-volume markets such as mobile phones and tablets. It's also happen... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency
By Kurt Shuler - 27 Aug, 2015 - Comments: 0

Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

The Week In Review: Design/IoT
By Jesse Allen - 07 Aug, 2015 - Comments: 0

Tools Cadence unveiled Joules, its new RTL power analysis solution. The tool performs design synthesis using a new integrated prototype mode of Cadence's Genus Synthesis product, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation. IP Synopsys and ASMedia completed a successful interoperability demonstration of Synopsys' USB 3.1 Devi... » read more

Emerging Security Protocols
By Ernest Worthman - 06 Aug, 2015 - Comments: 0

As the proliferation of mobile devices ramps up at escalating rates, securing these devices and the infrastructure they run on is becoming a top priority for both the hardware and the data that swirls within it. Traditional security platforms such as firewalls and antivirus programs are still a viable part of the security envelope, but the rapid emergence of zero-day/hour threats is somethin... » read more

Speeding Up Analog
By Ann Mutschler - 05 Aug, 2015 - Comments: 1

Semiconductor Engineering sat down to discuss analog design and how to speed up analog circuits with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What foll... » read more

Which Process, Material, IP?
By Ed Sperling - 30 Jul, 2015 - Comments: 1

For years chipmakers have been demanding more choices. They've finally gotten what they wished for—so many possibilities, in fact, that engineering teams of all types are having trouble wading through them. And to make matters worse, some choices now come with unexpected and often unwanted caveats. At the most advanced nodes it's a given that being able to shrink features and double patter... » read more

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