tag: Arteris

Different Approaches Emerge For Stacking Die
By Ed Sperling - 21 Aug, 2014 - Comments: 1

The concept of stacking die to shorten wires, improve performance, and reduce the amount of energy required to drive signals has been in research for at least the past dozen years at both IBM and Intel. And depending upon whom you ask, it could be another 2 to 10 years before it becomes a mainstream packaging approach—if it happens at all. At least part of the confusion stems from how you ... » read more

NoC Technology: Saving the Planet, One Chip at a Time
By Kurt Shuler - 21 Aug, 2014 - Comments: 0

In Silicon Valley, the cliché is that we are using technology to change the world in some meaningful way. However, I made some calculations recently and I found network-on-chip technology is actually contributing to efforts to reduce carbon emissions. SoC designers have become the ultimate energy misers as they strive to make tradeoffs between extending battery life and providing game-chang... » read more

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Blog Review: July 30
By Ed Sperling - 30 Jul, 2014 - Comments: 0

Mentor’s Colin Walls looks at a free collaborative online tool called codepad, which can be used for compiling, interpreting and executing code quickly. Free is good—sometimes. Cadence’s Brian Fuller followed a recent panel on high-speed, cross-fabric interface design, which focused on why designers need to consider chip, package and board to ensure signal and power integrity. So what... » read more

Apple CarPlay Vs. Android Auto
By Kurt Shuler - 25 Jul, 2014 - Comments: 1

The smartphone wars have been fought and won (well, at least for now), but now there’s a new electronics battle brewing in your garage, rather than your pocket. The talk of smartphone SoC technology proliferating from phones and into cars has finally transformed into action, and major electronics companies are striking deals with established automobile manufacturers to integrate the benefi... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

EDA’s Hedge Plays
By Ed Sperling - 24 Jul, 2014 - Comments: 0

While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

New Winners And Losers
By Brian Bailey - 24 Jul, 2014 - Comments: 0

During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

Where Do We Stand With CDC?
By Ann Mutschler - 18 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: What are the biggest use models for CDC verification today... » read more

The Week In Review: Design
By Ed Sperling - 17 Jul, 2014 - Comments: 0

Tools Cadence unveiled two new tools. The first is a rapid prototyping platform that the company claims will shorten bring-up time by 70%, with 4X improvements in capacity, with IEEE 1801 support for low-power verification through its emulation platform. The second is a single and multi-corner custom/analog extraction tool, which it claims will improve performance by 5X. The tool has been cert... » read more

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