tag: Arteris

Uncertainty Increases About What’s Next
By Ed Sperling - 24 Oct, 2013 - Comments: 0

Across the semiconductor industry, there is a lot of talk about what’s next. Lithography advances have stalled, NRE and mask costs are rising, and complexity is exploding. But unlike the 1 micron wall, which was supposed to be impenetrable, there is no single issue holding back progress. Instead, there are lots of them, most with pricey workarounds, but which together become more complicat... » read more

There’s A New Paradigm In Town
By Kurt Shuler - 24 Oct, 2013 - Comments: 0

I recently wrote an article in the October 9th issue of EETimes that appears to have rattled the semiconductor industry a bit. Entitled “Wake Up, Semi Industry: System OEMs Might Not Need You,” the article conveyed the fact that many system-level OEMs now have the capability — and desire — to develop their own application-specific chips. This may be news to many. But a simple review... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 10 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate marketing at Atrenta; ... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 04 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

Blog Review: Oct. 3
By Ed Sperling - 03 Oct, 2013 - Comments: 0

Cadence’s Brian Fuller rolls out a twice-monthly TV program called “Unhinged,” which he bills as a cross between The Daily Show, Letterman and ESPN. The intro is a classic. Who needs coffee? Synopsys’ Karen Bartleson interviews Bob Metcalfe, co-inventor of Ethernet, creator of Metcalfe’s Law—which has withstood the test of time quite well—on why Ethernet still really important.... » read more

New Architectures Redefining The Data Center
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling The cost of powering and cooling data centers, coupled with a better understanding of how enterprise-level applications can utilize hardware more effectively, are spawning a new wave of changes inside of data centers. Data centers are always evolving, but in this sector that evolution is deliberate and sometimes painstakingly slow. In fact, each major shift tends to last a de... » read more

More Rigor, Please
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor companies are embracing a single-platform strategy for their SoC designs, but sifting through the options can be quite a feat. While not wildly different from the traditional derivative approach, a single-platform strategy can mean different things to different companies. Sometimes it refers to a platform that is already successful in one application ... » read more

What Can Go Wrong?
By Kurt Shuler - 25 Sep, 2013 - Comments: 0

It’s no surprise that most corporate system-on-chip (SoC) design teams are dispersed throughout the world, with different functional teams often located in different countries and continents. For example, we have many customers whose SoC architecture is defined in the United States, but subsystems such as graphics and signal processing are designed elsewhere. Companies choose this approach in... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

Experts At The Table: Next-Generation IP Landscape
By Ann Mutschler - 30 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

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