Experts At The Table: Who Takes Responsibility?


By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

The Week In Review: Aug. 23


By Ed Sperling Cadence won a deal with Realtek, which licensed the Tensilica HiFi audio DSP core for voice recognition technology. Fast voice triggers have been possible for some time, but being able to combine that with low power for mobile devices isn’t easy because the devices are always on—or at least enough “on” to pick up voice commands. Mentor Graphics turned in a record-bre... » read more

The Single Platform Strategy


By Kurt Shuler For semiconductor companies in high-volume or emerging growth markets, the days of using multiple platforms to address different segments are over. The new era of using a single platform to address several different segments is rapidly taking hold. Adding fuel to this transition is the greater flexibility that design teams have to spin derivatives of those single platforms. T... » read more

Software Impact Grows


By Ed Sperling As the number of processors and processor cores increase in SoC, so does the amount of software. But unlike hardware, which grows linearly, software frequently grows exponentially. The great advantage of software is configurability—both before and after tapeout—yet it adds many more possible permutations and interactions that need to be worked out. And unlike the old PC m... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

The Week In Review: Aug. 16


By Ed Sperling Manufacturing Equipment giant Applied Materials added three extra letters company president Gary Dickerson’s title—CEO. Mike Splinter, who has served as the company’s CEO since 2003, will become executive chairman of the board of directors. Dickerson was the CEO of Varian, which Applied Materials acquired in 2011. Synopsys introduced a Dolby decoder for its ARC process... » read more

The Week In Review: July 26


By Ed Sperling Cadence’s Q2 revenue increased 11% to $362 million compared to $326 million in the same period in 2012. On a GAAP basis, net income dropped to $9 million compared with $36 million in 2012, but that decrease was impacted by the cost of recent acquisitions and integration of companies. On a non-GAAP basis, income was $61 million compared with $53 million in Q2 2012. Dassault... » read more

A Brief History Of The Interconnect


By Kurt Shuler The high functional integration of system-on-chip designs today is driving the need for new technological approaches in semiconductor design. Anyone who owns a Samsung Galaxy S4, HTC One or comparable smartphone can see the benefits of integrating onto one chip all the computing functions that were traditionally separate, discrete chips on a PC computer motherboard. For next-gen... » read more

3D IC Supply Chain: Still Under Construction


By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

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