tag: Arteris

New Reliability Issues Emerge
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Most consumers define reliability by whether a device turns on and works as planned, but the term is becoming harder to define as complexity increases and systems are interconnected. Adding more functionality in less space has made it more difficult to build complex chips, and it has made it more difficult to prevent problems in those chips. Verification coverage is a persist... » read more

Memory Gets Smarter
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

DAC Is Dead? Long Live DAC!
By Kurt Shuler - 27 Jun, 2013 - Comments: 0

By Kurt Shuler I have long decried the declining attendance at the ACM/EDAC/IEEE Design Automation Conference (DAC), especially in regard to this trend’s adverse effect on continuing professional education (CPE) opportunities for our industry’s engineers. (See my May 2011 article, “The Trouble With Tradeshows, for more.) In fact, for those of you who know me personally, I have sometimes ... » read more

The Week In Review: June 7
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling For all the hesitation about moving the Design Automation Conference to Austin, it turns out that Austin has a lot of hardware engineers. In fact they flooded into the conference, turning it into one of the most successful in recent years and setting new records in multiple areas. Even Texas Gov. Rick Perry showed up to see what all the fuss was about. Mentor Graphics added c... » read more

The Week In Review: May 31
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification pl... » read more

The X Factor
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market windows. Tools are available to deal with some of these unknowns, or X’s, but certainly not all of them. Moreover, no single tool can handle all unknowns, some of which can build upon other unkn... » read more

Just Add IP
By Kurt Shuler - 30 May, 2013 - Comments: 0

When discussing SoC design with my semiconductor design and software development peers, the conversation eventually gets around to the problem of, “There’s just too much IP!” The feelings I hear border on exasperation at the problem of integrating IP on today’s large SoCs. Engineers who were once paid to write lines of Verilog or C code from scratch are now spending much of their time t... » read more

The Analyst View
By Kurt Shuler - 25 Apr, 2013 - Comments: 0

By Kurt Shuler I was fortunate to be able to meet with 13 different semiconductor industry analysts from eight different companies over the last two weeks. Our conversations ranged from the current state of the semiconductor industry to future software architecture trends. I want to take this opportunity to thank them once again for the exchange of ideas and the opportunity to learn from them.... » read more

Diverging Viewpoints
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling The raw materials of semiconductor design include smart, well-trained people and money to fund good ideas from those people, whose backgrounds typically come from engineering, math, physics, computer science, materials science and sometimes even chemistry. While many experts, executives, and industry groups have been sounding the alarm in recent years about everything from la... » read more

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

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