The Week in Review: System-Level Design

Cadence unleashes power signoff tool; Synopsys teams with CEVA for DSP; Real Intent inks deal with NEC; Arteris wins deal with Schneider.


Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs.

Synopsys teamed up with CEVA to improve PPA for CEVA’s DSP cores with Synopsys’ high-performance core kit. According to the companies, CEVA improved performance by 8% in worst-case operating conditions for base-station applications using 28nm process technology.

Real Intent won a deal with NEC, which will use its tools for early detection of bugs in RTL. NEC plans to use the advance debugging for its communications systems.

Arteris won a deal with Schneider Electric, which is using its NoC IP for industrial control applications. In addition, Arteris is now ranked 144 among the fastest growing tech companies in North America, according to consulting giant Deloitte.

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