tag: Arteris

Experts At The Table: Next-Generation IP Landscape
By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

The Week In Review: Aug. 16
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Manufacturing Equipment giant Applied Materials added three extra letters company president Gary Dickerson’s title—CEO. Mike Splinter, who has served as the company’s CEO since 2003, will become executive chairman of the board of directors. Dickerson was the CEO of Varian, which Applied Materials acquired in 2011. Synopsys introduced a Dolby decoder for its ARC process... » read more

The Week In Review: July 26
By Ed Sperling - 26 Jul, 2013 - Comments: 0

By Ed Sperling Cadence’s Q2 revenue increased 11% to $362 million compared to $326 million in the same period in 2012. On a GAAP basis, net income dropped to $9 million compared with $36 million in 2012, but that decrease was impacted by the cost of recent acquisitions and integration of companies. On a non-GAAP basis, income was $61 million compared with $53 million in Q2 2012. Dassault... » read more

A Brief History Of The Interconnect
By Kurt Shuler - 25 Jul, 2013 - Comments: 0

By Kurt Shuler The high functional integration of system-on-chip designs today is driving the need for new technological approaches in semiconductor design. Anyone who owns a Samsung Galaxy S4, HTC One or comparable smartphone can see the benefits of integrating onto one chip all the computing functions that were traditionally separate, discrete chips on a PC computer motherboard. For next-gen... » read more

3D IC Supply Chain: Still Under Construction
By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

New Silos Form In IC Industry
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling For the past couple of decades corporations around the globe have been focused on down silos. In fact, it has become a mantra. It’s considered essential for making established corporations even more successful, and it’s almost always at the center of turnaround plans for troubled companies. Moreover, across a full spectrum of companies, it’s regularly cited by management c... » read more

Faster IP Integration
By Ed Sperling - 03 Jul, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down with Laurent Moll, chief technology officer at Arteris, to talk about interoperability, complexity and integration issues. What follows are excerpts of that conversation. SLD: What’s the big challenge with IP? Moll: Interoperability is always a concern. Because of ARM’s dominance, a lot of people are moving to AMBA protocols, whether that’... » read more

New Reliability Issues Emerge
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Most consumers define reliability by whether a device turns on and works as planned, but the term is becoming harder to define as complexity increases and systems are interconnected. Adding more functionality in less space has made it more difficult to build complex chips, and it has made it more difficult to prevent problems in those chips. Verification coverage is a persist... » read more

Memory Gets Smarter
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

DAC Is Dead? Long Live DAC!
By Kurt Shuler - 27 Jun, 2013 - Comments: 0

By Kurt Shuler I have long decried the declining attendance at the ACM/EDAC/IEEE Design Automation Conference (DAC), especially in regard to this trend’s adverse effect on continuing professional education (CPE) opportunities for our industry’s engineers. (See my May 2011 article, “The Trouble With Tradeshows, for more.) In fact, for those of you who know me personally, I have sometimes ... » read more

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