tag: Arteris

Interchip Connectivity
By Kurt Shuler - 31 Mar, 2011 - Comments: 0

By Kurt Shuler There has been a lot of confusion about the different standards for interchip connectivity, with many hardware developers of consumer electronics and mobile computing systems-on-chip wondering what to use. As an interconnect IP provider, I struggle with this every day when working with our customers. I wrote this article to share what I have learned. Why interchip connectivit... » read more

Experts At The Table: Billion-Gate Design Challenges
By Ed Sperling - 25 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excer... » read more

Widening The Channels
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Wide I/O—both as a specific memory standard and as a generic approach for on-chip networking—has been looked at for the past couple of chip generations as a way of improving SoC performance. Increasingly, it also is being used as a key strategy for reducing energy consumption. Wide I/O refers to a number of different approaches in on-chip networking, ranging from through-... » read more

Experts At The Table: Billion-Gate Design Challenges
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excer... » read more

Billion-Gate Chips
By Ed Sperling - 16 Mar, 2011 - Comments: 0

Low-Power Engineering examines hurdles ranging from power to cost in billion-gate IC designs with Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. [youtube vid=0jum2ThIVzg] » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 25 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is concurrent design strategic—meaning is it done at the architectural lev... » read more

Semiconductor M&A?
By Kurt Shuler - 24 Feb, 2011 - Comments: 0

Last week a friend of mine was giddy with joy as he exclaimed, “Semi M&A is back!” It seems Qualcomm’s acquisition of Atheros and Intel’s acquisition of Silicon Hive somehow changed the chemical makeup of his brain, transforming him from an eternal semiconductor market pessimist to a born-again optimist. Being someone who lives and dies by data, my initial response was, “Let’s s... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 18 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: Is there cross-training going on to allow for concurrent design? Brambilla... » read more

Concurrent Design
By Ed Sperling - 11 Feb, 2011 - Comments: 0

The idea of developing software and hardware simultaneously isn't new, but it has taken on renewed urgency in IC design because of growing complexity, including power and proximity issues. Low-Power Engineering captures the perspective of executives at four companies working in this market: Marco Brambilla of STMicroelectronics; Charlie Janac of Arteris; Mike Gianfagna of Atrenta, and Javier De... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 10 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: What is concurrent design and how has the definition changed? DeLaCruz: Th... » read more

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