Stacked Dies Gain Attention, But So Far Little Traction


By Ed Sperling For the better part of two decades there has been a steady stream of predictions about the abrupt end of Moore’s Law, but it now appears the formula for doubling the number of transistors on a die every couple years will simply dissipate rather than fall off a cliff. While companies such as Intel and IBM continue to develop road maps that extend their road maps all the wa... » read more

Making Connections


By Ed Sperling The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living. The numbe... » read more

To Bus Or Not To Bus, That Is The Question


By Ann Steffora Mutschler When you hear the words, “block interface,” your ears may not perk up, but as system architects well understand, making the right choice between a bus or non-bus interface on an SoC is absolutely critical to design’s success in terms of power efficiency, reusability and performance. How many of the problems in new chip designs have to do with the interconne... » read more

Pain Points At 22nm And Beyond


By Ed Sperling The roadmap for 22nm has a giant pothole in the middle of it. That hole is supposed to be filled by extreme ultraviolet lithography, or EUV. Instead it is being patched up using immersion lithography, which is about to cause some monumental headaches for design teams. The difference is comparable to a surgeon using a chainsaw instead of a scalpel. The cut isn’t nearly as ... » read more

NoC Your SoCs Off


By Ed Sperling The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide. This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological a... » read more

The Quest For Faster Data Throughput On A Chip


By Ed Sperling As with all network topologies, the general rule is the faster the better. Jack Browne, VP of sales and marketing at Sonics, said his customers are asking for higher-speed interconnects. “Right now we’re at 300MHz,” he said. “They want to more than double that in the very near future and eventually get to 1GHz.” Getting to that speed is no simple ... » read more

Making A Multicore System Work


Making all the pieces work together in a multicore system requires a deep understanding of the technology, lots of different layers of synthesis, and some incredibly complex testing strategies.   System-Level Design sat down with James Aldis, system on chip architect for Texas Instruments wireless business unit; Charles Janac, president and CEO of Arteris, Drew Wingard, CTO of Sonics, and ... » read more

Making A Multicore System Work


If you think designing a single-core system is hard, designing multicore systems is multiple times harder. Connecting all the pieces together and making them work properly, if not together, is one of the hardest tasks design engineers and architects will ever face. System-Level Design tracked down some of the experts in this field and sat them down around a table to discuss what’s going... » read more

New Pain Points In System-Level Design


By Ed Sperling One of the strange things about downturns is they force companies to re-examine what they do and question what kind of value they bring to the market. This is particularly true in the semiconductor world, where the average selling prices for chips has been sliding for the better part of two decades. In the case of the chip industry, which is heavily cyclical, that leaves lo... » read more

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