tag: ASE

Scaling Bump Pitches In Advanced Packaging
By Mark LaPedus - 25 Oct, 2021 - Comments: 0

Interconnects for advanced packaging are at a crossroads as an assortment of new package types are pushing further into the mainstream, with some vendors opting to extend the traditional bump approaches while others roll out new ones to replace them. The goal in all cases is to ensure signal integrity between components in IC packages as the volume of data being processed increases. But as d... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 15 Oct, 2021 - Comments: 0

Chipmakers TSMC posted its results for the quarter and confirmed its long-awaited plans to build a fab in Japan. It’s not a leading-edge fab, but rather a plant for 28nm/22nm processes. “The company confirmed plans to build a new fab in Japan for 22nm + 28nm,” said Aaron Rakers, an analyst at Wells Fargo, in a research note. “An average 22/28nm fab costs ~$4-5B range per 45k wspm. Fab ... » read more

PCB And IC Technologies Meet In The Middle
By Bryon Moyer - 12 Oct, 2021 - Comments: 1

Surface-mount technology (SMT) is evolving far beyond its roots as a way of assembling packaged chips onto printed circuit boards without through-holes. It is now moving inside packages that will themselves be mounted on PCBs. But SMT for advanced packages isn’t the same as the SMT we’ve been used to. “Many systems include multiple ASICs, a lot of memory, and that's all integrated i... » read more

Fan-Out And Packaging Challenges
By Mark LaPedus - 06 Oct, 2021 - Comments: 2

Semiconductor Engineering sat down to discuss various IC packaging technologies, wafer-level and panel-level approaches, and the need for new materials with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of globa... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 17 Sep, 2021 - Comments: 0

Packaging and test Advantest and PDF Solutions have launched their first jointly developed offering since forming a partnership in 2020. The new product is called the Advantest Cloud Solutions Dynamic Parametric Test (ACS DPT) solution. It integrates PDF Solutions’ Exensio portfolio of data analytics with Advantest’s V93000 Parametric Test System. The ACS DPT solution is designed to op... » read more

System-In-Package Thrives In The Shadows
By Mark LaPedus - 16 Sep, 2021 - Comments: 0

IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

Challenges With Chiplets And Packaging
By Mark LaPedus - 15 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 10 Sep, 2021 - Comments: 0

Chipmakers, OEMs Intel plans to establish foundry capacity at its fab in Ireland. The company has also launched the so-called Intel Foundry Services Accelerator to help automotive chip designers transition from mature to advanced nodes. The company is setting up a new design team and offering both custom and industry-standard intellectual property (IP) to support the needs of automotive custom... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Aug, 2021 - Comments: 0

Chipmakers, OEMs Reports have surfaced that TSMC has delayed its 3nm process. But TSMC says the technology remains on track. Volume production for TSMC’s 3nm is still scheduled for the second half of 2022. On the flip side, there is speculation that TSMC may increase its wafer prices by up to 20%, according to a report from the Taipei Times. Here's another report. This is due to chip shortag... » read more

Manufacturing Bits: Aug. 24
By Mark LaPedus - 24 Aug, 2021 - Comments: 0

Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more

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