Post-Quantum Computing Threatens Fundamental Transport Protocols

By Karen Heyman - 01 Aug, 2024 - Comments: 0

The Transport Level Security (TLS) protocol is one of the few rock-steady spots in the rapidly changing computing industry, but that's about to change as quantum computers threaten traditional encryption schemes. Because TLS is fundamental to network communications, including allowing Internet of Things (IoT) devices to function properly, researchers already are exploring both hardware and s... » read more

Applying Machine Learning to EDA, FPGA Design Automation Tools

By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas Dallas. Abstract: "With the recent advances in hardware technologies like advanced CPUs and GPUs and the large availability of open-source libraries, machine learning has penetrated various domains, including Electronics Design Automation (EDA). E... » read more

Programmable HW Accelerators For BGV Fully Homomorphic Encryption In The Cloud

By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “BASALISC: Programmable Hardware Accelerator for BGV Fully Homomorphic Encryption” was published by researchers at COSIC KU Leuven, Galois Inc., and Niobium Microsystems. Abstract: "Fully Homomorphic Encryption (FHE) allows for secure computation on encrypted data. Unfortunately, huge memory size, computational cost and bandwidth requirements limit its practic... » read more

A Chiplet-Based Supercomputer For Generative LLMs That Optimizes Total Cost of Ownership

By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models" was published by researchers at University of Washington and University of Sydney. Abstract: "Large language models (LLMs) such as ChatGPT have demonstrated unprecedented capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant factor limiting ... » read more

Circuit Design For Industry 4.0

By Bjorn Zeugmann - 11 May, 2023 - Comments: 0

By Björn Zeugmann and Olaf Enge-Rosenblatt The digitalization of industry is progressing in leaps and bounds, albeit not at the same speed everywhere. In many industries, processes can be digitalized well to very well — for example, because electronic control systems can be retrofitted from analog to digital relatively easily. In some cases, new industries emerge only because processes ha... » read more

Week In Review: Manufacturing, Test

By Karen Heyman - 24 Mar, 2023 - Comments: 0

TEL announced plans to build a ¥2.2 billion ($168.2 million) production and logistics center at its Tohoku Office to increase capacity. Construction of the 57,000m² facility, which will be used for manufacturing thermal processing and single-wafer deposition systems, is slated to start in spring 2024, and expected to be completed in fall 2025. Toshiba's board voted in favor of a 2 trillio... » read more

FPGAs: Automated Framework For Architecture-Space Exploration of Approximate Accelerators

By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A technical paper titled "autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems" was published (preprint) by researchers at TU Wien, Brno University of Technology, and NYUAD. Abstract "Generation and exploration of approximate circuits and accelerators has been a prominent research domain exploring energy-efficiency and/or performance... » read more

Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)

By Technical Paper Link - 12 Dec, 2022 - Comments: 0

A new technical paper titled "CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework" was published by researchers at Princeton University and Stanford University. "Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either... » read more

Bespoke Silicon Redefines Custom ASICs

By Ann Mutschler - 28 Jul, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss bespoke silicon and what's driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens... » read more

Design of a Mixed-signal ASIC for the front-end electronics of ionisation chambers

By Technical Paper Link - 23 May, 2022 - Comments: 0

New technical paper titled "An Ultra Low Current Measurement Mixed-Signal ASIC for Radiation Monitoring Using Ionisation Chambers," by researchers at CERN. Abstract "Measurement of total ionizing dose in a radiation field is efficiently carried out by ionisation chambers. The paper details the design of a mixed-signal ASIC for the front-end electronics of ionisation chambers. A single c... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: ASIC