tag: Atrenta

Where Do We Stand With CDC?
By Ann Mutschler - 26 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: While not a new aspect of design, clock domain crossing is... » read more

Tougher Memory Choices
By Brian Bailey - 23 Jun, 2014 - Comments: 1

In part 1 of this roundtable, the participants talked about the investments being made in memory technologies, the role that memories play in system security and the tools support for optimizing memory architecture. Taking part in the conversation are Herbert Gebhart vice president of interface and system solutions in the Memory and Interfaces Division of Rambus, Bernard Murphy, chief technolog... » read more

Blog Review: June 18
By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

Does EDA Consider RTL Power Optimization As Job Done?
By Mark Baker - 13 Jun, 2014 - Comments: 0

The “Power Buzz” leading into this year’s Design Automation Conference was around System Level Power Architecture and Optimization—some would say the natural progression of EDA towards the next big customer design challenge. This does beg the question of whether EDA considers RTL Power Optimization a mature solution. All products or solutions progress through various stages of maturity,... » read more

Do SoCs Need Earthquake Insurance?
By Ann Mutschler - 13 Jun, 2014 - Comments: 1

RTL sign-off is not a new term, but with SoCs that can be comprised of up to 90% IP blocks combined with the complexities that advanced manufacturing process nodes bring, RTL sign-off activities become a process that demands a more comprehensive approach. “There is a fundamental shift going on in chip design in general in that there is a bigger focus on so-called system on chip (SoC) desig... » read more

S-L Power Modeling Gains Steam
By Ann Mutschler - 12 Jun, 2014 - Comments: 1

Power analysis, architectural exploration and optimization of an SoC is a hot topic of discussion today. It is well accepted this must be addressed at a higher level of abstraction because not just the hardware must be taken into account with power intent and power management structures. It has to be viewed from a system point of view, as well, where the hardware resides along with the opera... » read more

Tougher Memory Choices
By Brian Bailey - 12 Jun, 2014 - Comments: 1

Memories have become a hot topic, so Semiconductor Engineering sat down with experts during DAC to discuss some of the issues. Taking part in the conversation were Herbert Gebhart vice president of interface and system solutions in the Memory and Interfaces Division of Rambus, Bernard Murphy, chief technology officer for Atrenta; Patrick Soheili, vice president and general manager for IP Soluti... » read more

What’s Wrong With Power Signoff
By Ed Sperling - 12 Jun, 2014 - Comments: 0

Reducing power has emerged as the most pressing issue in the history of technology. On one hand, it’s the biggest opportunity the electronics industry has ever seen. On the other, the abuse of cheap power has been linked to global warming, human catastrophe, and geopolitical strife. In all cases, the semiconductor increasingly finds itself at the vortex of all of this, and making chips more e... » read more

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

Chip Security Impacts Power, Performance
By Ann Mutschler - 05 Jun, 2014 - Comments: 1

We know that hackers are getting more sophisticated all the time to the point that it may already be possible to gain access to an automobile without touching it. According to this Financial Times article, with new cars containing an increasing number of connected applications – everything from music streaming services and Bluetooth to email readers and likely even GPS systems – it leaves t... » read more

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