BEOL Integration For The 1.5nm Node And Beyond

By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

More Manufacturing Issues, More Testing

By Ed Sperling - 08 Feb, 2022 - Comments: 0

Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

Nontraditional Post Develop Inspection And Review Strategy For Via Defects

By KLA - 18 Dec, 2017 - Comments: 0

A viable in-line monitor for missing vias in the back end of line (BEOL) has traditionally been challenging due to the nature of the defects. Today’s available solutions do not meet the requirements of a true in-line and at-level monitor strategy. These solutions either indirectly monitor the defect further down the line, put production at risk of damage or contamination due to exceeding stri... » read more

BEOL Issues At 10nm And 7nm (part 2)

By Ed Sperling - 04 Jan, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

BEOL Issues At 10nm And 7nm (Part 1)

By Ed Sperling - 15 Dec, 2016 - Comments: 5

Faster Time To Yield

By Ed Sperling - 23 Aug, 2016 - Comments: 2

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. SE: Why does it take so long to get a chip all the way through to manufacturing? Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new th... » read more

Pain Points At 7nm

By Ed Sperling - 24 Mar, 2016 - Comments: 3

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

EUV: Cost Killer Or Savior?

By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

The Fill Ecosystem Evolves Again

By Jeff Wilson - 23 Jul, 2015 - Comments: 0

Several years ago, we wrote about the ecosystem of fill, and how 20nm technology required a much tighter relationship between the foundry, designers and EDA vendors. While the players remain the same, there have been some interesting shifts in fill techniques and usage as designers move to even-smaller technologies. What continues with each node is the additional complexity of the design flo... » read more

Addressing Thin Film Thickness Metrology Challenges Of 14nm BEOL Layers

By KLA - 21 May, 2015 - Comments: 0

This paper describes a method to effectively monitor the film stack at different metal CMP process steps using a spectroscopic ellipsometer metrology tool. By proper modeling of the Cu dispersion and simulating the underlayer film information underneath the Cu pad, a single measurement recipe was developed which can be used to monitor each process step in the metal CMP process with stable and r... » read more

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Knowledge Centers
Entities, people and technologies explored

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tag: back end of line