Chip Industry Technical Paper Roundup: Sept. 17


New technical papers recently added to Semiconductor Engineering’s library: [table id=356 /] More ReadingTechnical Paper Library home » read more

3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)


A new technical paper titled "TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path" was published by researchers at Pohang University of Science and Technology and Baum Design Systems. Abstract "In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D I... » read more

Startup Funding: December 2022


The month of December saw six rounds of $100 million or more. The largest, at a massive half-billion dollars, will support manufacturing of 12-inch monocrystalline silicon polished wafers and epitaxial wafers in China. The company is aiming for a production rate of 1 million pieces a month when current expansion is completed. Also in the half-billion club last month is a company making auton... » read more