Analog Simulation At 7/5/3nm

By Ed Sperling - 27 Jan, 2020 - Comments: 0

Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip. » read more

Making Models Interoperable

By Ann Mutschler - 20 Nov, 2014 - Comments: 0

As engineering teams raise the vision of their design to a higher level of abstraction, the use of behavioral modeling is growing. While not ubiquitous, the concepts are gelling, which at least is helping the industry discuss the technology more intelligently and determine where automation makes sense. One of the biggest concerns with behavioral modeling is what engineering teams want to do ... » read more

Filling In The Gaps For Mixed-Signal Verification

By Ann Mutschler - 24 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal [getkc id="10" kc_name="Verification"] with Haiko Morgenstern, Mixed-Signal Verification Group Staff Engineer at Infineon; Dr. Gernot Koch, CAD Manager at Micronas; Pierluigi Daglio, AMS Design Verification Flows Manager at STMicroelectronics; and Helene Thibieroz, AMS marketing manager at [getentity id="22035" comment="Synopsys"]. What... » read more

The Growing Need For Behavioral Modeling

By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to behavioral or functional modeling, there is an inherent notion of function, architecture and interconnect. This approach has long been considered a future requirement, but in complex designs the future part no longer applies. Behavioral modeling is a way of isolating or abstracting out a key part of the architectural description and making sure i... » read more

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Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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tag: behavioral modeling

Analog Simulation At 7/5/3nm

Making Models Interoperable

Filling In The Gaps For Mixed-Signal Verification

The Growing Need For Behavioral Modeling

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