Closing The Loop: Meeting High-Frequency Power Demands With Decoupling Capacitors

By Cadence - 06 Jul, 2022 - Comments: 0

The inability to supply adequate power in time can result in intermittent board failure and hours troubleshooting in the lab. Even an IC with ample current supply can experience "power shortage" if the energy needed to transmit the data bitstream isn't available in time. Click here to read more. » read more

Introducing mPower

By Siemens EDA - 13 Oct, 2021 - Comments: 0

Power integrity analysis evaluates circuits to determine if they will provide their designed/intended performance and reliability as implemented. Designers must be able to verify analog and digital power integrity from the RTL/gate-level through die-level integrations up to the package and board system-level. The mPower toolset is an innovative power integrity verification solution that brings ... » read more

Demystifying Mirror Types

By Tyler Lockman - 12 Mar, 2020 - Comments: 0

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of mirroring which are used in different places. Often, I get questions about what, exactly, those differences are. And even more, why the styles are used for d... » read more

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tag: board

Closing The Loop: Meeting High-Frequency Power Demands With Decoupling Capacitors

Introducing mPower

Demystifying Mirror Types