Clocks Getting Skewed Up


At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it's fraught with the most problems at the physical level. To some, the clock is the AC power supply of the chip. To others, it is an analog network almost beyond analysis. Ironically, there are no languages to describe clocking, few tools t... » read more

Missing Interposer Abstractions And Standards


The design and analysis of an SoC based on an interposer is not for the faint of heart today, but the industry is aware of the challenges and is attempting to solve them. Until that happens, however, it will be a technique that only large companies can deploy because they need to treat everything almost as if it were a single die. The construction of large systems uses techniques, such as ab... » read more

Waiting For Chiplet Standards


The need and desire for chiplets is increasing, but for most companies that shift will happen slowly until proven standards are in place. Interoperability and compatibility depend on many layers and segments of the supply chain coming to agreement. Unfortunately, fragmented industry requirements may lead to a plethora of solutions. Standards always have enabled increasing specialization. ... » read more

The Good And Bad Of Chiplets


The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

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