tag: Breker

Can AI Create Missing Models?
By Brian Bailey - 11 Jun, 2026 - Comments: 0

Key takeaways Models are an essential part of EDA flows, each capturing necessary detail while retaining good execution performance. Models have been expensive to create, maintain and verify, restricting their utilization, but AI may be able to significantly reduce their cost. A deeper question remains. Should AI be used to create models that help existing flows, or should AI be used... » read more

A New Era For Co-Processing
By Brian Bailey - 09 Apr, 2026 - Comments: 0

Key Takeaways: There is no single processor capable of executing everything efficiently, meaning that multiple processors are required. Maximum efficiency is gained by minimizing the movement of data. Architects must maximize efficiency for today's workloads, while also adding enough flexibility to handle tomorrow's. New processor architectures are rapidly evolving thanks to... » read more

Does Your RISC-V Core Meet The Standard?
By Brian Bailey - 29 Jan, 2026 - Comments: 0

Key Takeaways Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables flexibility, there is a potential for ecosystem fragmentation. It is mathematically impossible to test every instruction combination, so engineers are moving beyond just "bl... » read more

AI Plays Multiple Roles Within EDA
By Brian Bailey - 25 Nov, 2025 - Comments: 0

AI's infusion into our world may seem sudden and unexpected, but EDA has been quietly adopting it for more than a decade. What's changed is that it's now becoming more visible, thanks to increasingly powerful large language models (LLMs) and the need to apply them to increasingly challenging multi-physics problems. Two fundamental shifts underlie AI's increasing prominence. First, heat is be... » read more

RISC-V Profiles Help Conformance
By Brian Bailey - 18 Dec, 2024 - Comments: 0

Experts At The Table: What's needed to be able to trust that a RISC-V implementation will work as expected across multiple designs using standard OSes. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeist... » read more

RISC-V’s Software Portability Challenge
By Brian Bailey - 13 Nov, 2024 - Comments: 0

Experts At The Table: RISC-V provides a platform for customization, but verifying those changes remains challenging. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeister, executive director for strategi... » read more

Verification Tools Straining To Keep Up
By Brian Bailey - 01 Jul, 2024 - Comments: 0

Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

Blog Review: June 19
By Jesse Allen - 19 Jun, 2024 - Comments: 0

Siemens' John McMillan and Todd Burkholder suggest using an automatic formal-based approach to verifying chiplet package connections early in the design process. Cadence's Veena Parthan explores the intricacies of wind tunnel testing in automotive design and how the collaborative relationship between computational fluid dynamics (CFD) and wind tunnels has resulted in accelerated and more nua... » read more

RISC-V Heralds New Era Of Cooperation
By Brian Bailey - 30 May, 2024 - Comments: 0

RISC-V is paving the way for open source to become accepted within the hardware community, creating a level of industry collaboration never seen in the past, while revitalizing the connection between academia and industry. The big question is whether this arrangement is just a placeholder while the industry re-learns how to develop processors, or whether this processor architecture is someth... » read more

Trouble Ahead For IC Verification
By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

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