tag: Breker

IC Security Issues Grow, Solutions Lag
By Ed Sperling - 24 Apr, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the growing chip security threat and what's being done to mitigate it, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker V... » read more

What Does 2023 Have In Store For Chip Design?
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Selecting The Right RISC-V Core
By Brian Bailey - 16 Jan, 2023 - Comments: 0

With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either commercially or in open-source form, end users face an increasingly difficult challenge of ensuring they make the best choices. Each user likely will have a set of needs and concerns that almost equals th... » read more

AI-Powered Verification
By Brian Bailey - 01 Jun, 2022 - Comments: 1

With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

The High But Often Unnecessary Cost Of Coherence
By Brian Bailey - 22 Dec, 2021 - Comments: 3

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized accelerators and other processing elements. While cache coherency won't disappear anytime soon, it is increasingly being viewed as a luxury necessary to preserve a long-standing programming paradig... » read more

Will Open-Source Processors Cause A Verification Shift?
By Ann Mutschler - 19 Dec, 2019 - Comments: 0

While the promised flexibility of open source could have advantages and possibilities for processors and SoCs, where does the industry stand on verification approaches and methodologies from here? Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows... » read more

Extending Portable Stimulus
By Brian Bailey - 16 Oct, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSpin... » read more

Solving The Memory Bottleneck
By Brian Bailey - 04 Oct, 2019 - Comments: 4

Chipmakers are scrambling to solve the bottleneck between processor and memory, and they are turning out new designs based on different architectures at a rate no one would have anticipated even several months ago. At issue is how to boost performance in systems, particularly those at the edge, where huge amounts of data need to be processed locally or regionally. The traditional approach ha... » read more

Are Digital Twins Something For EDA To Pursue?
By Ann Mutschler - 07 Aug, 2019 - Comments: 0

‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing th... » read more

Open Source Processors: Fact Or Fiction?
By Brian Bailey - 27 Jun, 2019 - Comments: 3

Open source processors are rapidly gaining mindshare, fueled in part by early successes of RISC-V, but that interest frequently is accompanied by misinformation based on wishful thinking and a lack of understanding about what exactly open source entails. Nearly every recent conference has some mention of RISC-V in particular, and open source processors in general, whether that includes keyno... » read more

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