tag: Breker Verification Systems

An Architectural Choice Overdue For Change
By Brian Bailey - 04 Dec, 2014 - Comments: 0

The past appears to be a lot simpler than the present and when we look into the future, the right decisions often look highly uncertain. This is the value of hindsight, but also includes the notion that the winner gets to write history. What semiconductors look like today could have been very different if different decisions had been made 20 years ago. What if the industry had adopted a paralle... » read more

Blog Review: July 23
By Ed Sperling - 23 Jul, 2014 - Comments: 0

Mentor’s John Day says that within the decade you will be able to contact a real person from your car. Hopefully that doesn't mean marketing people will be able to contact you while you’re stuck in traffic. Cadence’s Brian Fuller says the future of EDA in the automotive market isn’t just about chips. Think security, software and cost reduction. It’s not just SoCs that are going ... » read more

Executive Insight: Adnan Hamid
By Brian Bailey - 22 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization. ... » read more

Blog Review: May 14
By Ed Sperling - 14 May, 2014 - Comments: 0

Ansys’ Bill Vandermark highlights the top five engineering articles of the week. Of particular note is element No. 117, a new entry in the periodic table. The temporary name is ununseptium, which means…well, surprise…117. Cadence’s Brian Fuller follows a panel discussion about the biggest potential roadblock for the IoT’s success—privacy and security. You’ve been warned. Syn... » read more

Graphing Toward Standardization
By Brian Bailey - 24 Apr, 2014 - Comments: 0

Graph-based verification has become the hot topic of the day. It commanded a lot of attention at the recent DVCon, promises to fix many of the problems plaguing functional verification, can provide an automated way to perform system-level verification, enables portability of tests between simulation, emulation and prototyping, reduces the wastage created by constrained random test pattern gener... » read more

Big Shift In SoC Verification
By Ed Sperling - 31 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

EDA Shapes Its Future
By Brian Bailey - 27 Mar, 2014 - Comments: 2

In part one of this series, Semiconductor Engineering looked at growth within the EDA industry and the types of approaches being made to expand the scope of the markets that they serve. Scope expansion comes from the creation of new tools, the growth of companies in the IP space and the various ways in which opportunities can be found in new markets. Additional growth opportunities come from so... » read more

Biggest Verification Mistakes
By Ann Mutschler - 27 Mar, 2014 - Comments: 0

[getkc id="81" kc_name="SoC"]s today have more processors and more embedded software than ever, including drivers and middleware just to get the hardware working. This, in turn, requires more and better [getkc id="10" kc_name="verification"]. Add to the challenge the fact that there is no one way to do verification and it is easy to comprehend how critical it is to for hardware and software tea... » read more

Enabling Test Portability With Graphs
By Ann Mutschler - 20 Mar, 2014 - Comments: 0

Is it time to move up again? When it comes to test portability between simulation, emulation, prototypes and silicon, as well as an easier way to create a test structure, the answer appears to be a resounding ‘Yes.’ Looking at these activities from a higher level of abstraction and using a graph-based approach should allow automation where there has been none previously, and could allow val... » read more

Big Shift In SoC Verification
By Ed Sperling - 17 Mar, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

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