tag: Broadcom

Roundtable: Lower-Power Chips
By Ed Sperling - 08 Nov, 2012 - Comments: 0

Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta. [youtube vid=cD560pgEegk] » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What are ... » read more

Quantum Shifts
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ed Sperling Intel, STMicroelectronics and some of the leading memory providers already are working on 10nm process technology, and advanced researchers in universities and industry-leading companies are looking at 7nm, 5nm and even beyond. Those who have glimpsed this technological future have similar observations. There is no single technology problem that has to be solved at these node... » read more

Moore’s Law Revisited
By Ed Sperling - 25 Oct, 2012 - Comments: 0

It’s no surprise that Moore’s Law can continue for many more generations. Intel’s road map already extends down to 5nm, most likely with carbon nanotube FETs, tunnel FETs, graphene TSVs and maybe even fully depleted SOI to replace bulk CMOS. The rest of the industry has been hanging back a node or two, gliding on the coattails of what Intel and companies like IBM, Samsung and STMicroel... » read more

Firms Rethink Fabless-Foundry Model
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

Packaging Tradeoffs More Complex Than Ever
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

Too Many Standards, But Still Not Enough
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ed Sperling The semiconductor industry has been one of the most prolific sectors in history when it comes to generating standards. Talk to any design engineer facing time-to-market pressures, new packaging approaches, and a mindboggling number of merchant IP, subsystems and interface requirements, and you’ll hear a compelling pitch for new standards. Talk to his or her boss and you’ll p... » read more

Experts At The Table: Are We Cool?
By Ed Sperling - 08 Jul, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation. LPE: Has there been any pr... » read more

Experts At The Table: Are We Cool?
By Ed Sperling - 24 Jun, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation. LPE: How do we get the mes... » read more

Experts At The Table: Are We Cool?
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation. LPE: At 28nm we have clock ... » read more

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