Moore’s Law Revisited


It’s no surprise that Moore’s Law can continue for many more generations. Intel’s road map already extends down to 5nm, most likely with carbon nanotube FETs, tunnel FETs, graphene TSVs and maybe even fully depleted SOI to replace bulk CMOS. The rest of the industry has been hanging back a node or two, gliding on the coattails of what Intel and companies like IBM, Samsung and STMicroel... » read more

Firms Rethink Fabless-Foundry Model


By Mark LaPedus As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model. Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the found... » read more

Packaging Tradeoffs More Complex Than Ever


By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

Too Many Standards, But Still Not Enough


By Ed Sperling The semiconductor industry has been one of the most prolific sectors in history when it comes to generating standards. Talk to any design engineer facing time-to-market pressures, new packaging approaches, and a mindboggling number of merchant IP, subsystems and interface requirements, and you’ll hear a compelling pitch for new standards. Talk to his or her boss and you’ll p... » read more

Experts At The Table: Are We Cool?


By Ed Sperling Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation. LPE: Has there been any pr... » read more

Experts At The Table: Are We Cool?


By Ed Sperling Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation. LPE: How do we get the mes... » read more

Experts At The Table: Are We Cool?


By Ed Sperling Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation. LPE: At 28nm we have clock ... » read more

Power Changes Everything


By Ann Steffora Mutschler Optimizing design methodologies for effective power utilization sometimes meaning throwing out old ideas and approaches and starting fresh. This is exactly what wireless chip giant Broadcom did in its quest to manage power in its chips. Low-Power Engineering spoke with Michael Hurlston, vice president of the mobile wireless group at Broadcom, to discuss current and f... » read more

Keeping Up With Complexity


By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

The Missing Pieces In Power Modeling—And Who’s Going To Provide Them


By Ed Sperling The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power. Providing these kind of models is easier said than done, however. Creating an accurate power model requires accurate data from all the other pieces on a chip that potentially can affect the power. That includes how third-party ... » read more

← Older posts Newer posts →