tag: cache coherency

What Can Go Wrong In Automotive
By Ed Sperling - 17 Jan, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Tuning Heterogeneous SoCs
By Brian Bailey - 08 Dec, 2016 - Comments: 0

It's one thing to pack multiple processor cores into a design, but it is much more difficult to ensure the hardware matches the software's requirements, or that the software optimally uses the hardware. Both the hardware and software teams are now facing these issues, and there are few tools to help them fully understand the problems or to provide solutions. Design teams continue to add more... » read more

Executive Insight: Sundari Mitra
By Ed Sperling - 20 Sep, 2016 - Comments: 0

Sundari Mitra, co-founder and CEO of [getentity id="22535" e_name="NetSpeed Systems"], sat down with Semiconductor Engineering to discuss machine learning, shifting from a processor-centric to a memory-centric design, and what needs to change to make that all happen. What follows are excerpts of that conversation. SE: What is the biggest change you’re seeing? Mitra: We go through a cycl... » read more

The Real Value Of Digital Horsepower
By Ed Sperling - 08 Sep, 2016 - Comments: 0

Chipmakers and systems vendors are beginning to experiment with a slew of new ways to beef up performance and reduce power and area, now that shrinking features no longer guarantees those improvements. The number of new ideas introduced at industry conferences in the past few months is almost mind-boggling. Just on the CPU side there are new architectures that improve the amount of work that... » read more

Embedded Evolution
By Brian Bailey - 26 Aug, 2016 - Comments: 1

The design of embedded systems has changed drastically from the days when I was directly involved with them. My first job after leaving college was to design aircraft control systems. I had the dubious honor to be working on the first civilian fly-by-wire aircraft – the Airbus A310. The reason I say dubious is that we had so many eyes trained on us, and that system contained so much redundanc... » read more

All You Need Is Cache (Coherency) To Scale Next-Gen SoC Performance
By Kurt Shuler - 25 Aug, 2016 - Comments: 0

Life on the SoC performance front remains a withering battle sometimes, because things can seem fairly bleak. As transistor scaling becomes more expensive below 10-nanometer feature sizes, every day it becomes harder to double performance every 18-months or so and stay competitive. Nowhere is the pain of this battle more acute than in consumer and automotive systems, where low cost is the key t... » read more

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP
By Arteris - 24 Aug, 2016 - Comments: 0

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication bet... » read more

How Cache Coherency Impacts Power, Performance
By Ann Mutschler - 27 Jul, 2016 - Comments: 0

As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the fastest they can, putting pressure on the CPU complex to manage all of the requests. Until a generation ago, it was okay for the CPU to control that memory and have access to it, as well as be t... » read more

How Cache Coherency Impacts Power, Performance
By Ann Mutschler - 18 Jul, 2016 - Comments: 2

Managing how the processors in an SoC talk to one another is no small feat, because these chips often contain multiple processing units and caches. Bringing order to these communications is critical for improving performance and [getkc id="106" kc_name="reducing power"]. But it also requires a detailed understanding of how data moves, the interaction between hardware and software, and what c... » read more

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