tag: Cadence Design Systems

DRAM Thermal Issues Reach Crisis Point
By Karen Heyman - 09 Jun, 2022 - Comments: 5

Within the DRAM world, thermal issues are at a crisis point. At 14nm and below, and in the most advanced packaging schemes, an entirely new metric may be needed to address the multiplier effect of how thermal density increasingly turns minor issues into major problems. A few overheated transistors may not greatly affect reliability, but the heat generated from a few billion transistors does.... » read more

Removing Barriers For End-To-End Analytics
By Anne Meixner - 07 Jun, 2022 - Comments: 0

Parties are coming together, generating guidelines for sharing data from IC design and manufacturing through end of life, setting the stage for true end-to-end analytics. While the promise of big data analytics is well understood, data sharing through the semiconductor supply chain has been stymied by an inability to link together data sources throughout the lifecycle of a chip, package, or ... » read more

AI-Powered Verification
By Brian Bailey - 01 Jun, 2022 - Comments: 1

With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

EDA Software Design Flow Considerations For The RF/Microwave Module Designer
By Cadence - 25 May, 2022 - Comments: 0

Miniaturization of consumer products, aerospace and defense systems, medical devices, and LED arrays has spawned the development of a technology known as the multi-chip module (MCM), which combines multiple integrated circuits (ICs), semiconductor die, and other discrete components within a unifying substrate for use as a single component. This white paper outlines the steps for implementing an... » read more

The Challenge Of Optimizing Chip Architectures For Workloads
By Brian Bailey - 12 May, 2022 - Comments: 1

It isn't possible to optimize a workload running on a system just by looking at hardware or software separately. They need to be developed together and intricately intertwined, an engineering feat that also requires bridging two worlds with have a long history of operating independently. In the early days of computing, hardware and software were designed and built by completely separate team... » read more

Improving PPA With AI
By John Koon - 12 May, 2022 - Comments: 0

AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

Building Security Into ICs From The Ground Up
By John Koon - 05 May, 2022 - Comments: 0

Cyberattacks are becoming more frequent and more sophisticated, but they also are starting to compromise platforms that until recently were considered unbreakable. Consider blockchains, for example, which were developed as secure, distributed ledger platforms. All of them must be updated with the same data for a transaction to proceed. But earlier this year a blockchain bridge platform calle... » read more

Data Management Position: An Automated Approach to Intelligent PCB Design Data Management
By Cadence - 04 May, 2022 - Comments: 0

The design cycle of electronic devices produces vast amounts of data. From a top-level view, this data can be broken down into basic blocks, including software, circuit board design, mechanical design, and others. These blocks contain extensive and complex information, including the types and amounts of individual data and information files, as well as their hierarchy structure. This data and i... » read more

The Challenges Of Incremental Verification
By Brian Bailey - 28 Apr, 2022 - Comments: 1

Verification consumes more time and resources than design, and yet little headway is being made to optimize it. The reasons are complex, and there are more questions than there are answers. For example, what is the minimum verification required to gain confidence in a design change? How can you minimize the cost of finding out that the change was bad, or that it had unintended consequences? ... » read more

Advances In EM Analysis And Design Flows For RF System Development
By Cadence - 27 Apr, 2022 - Comments: 0

With the move toward higher frequencies and component densities, RF/mixed signal PCB systems and heterogeneous system-in-package (SiP) technologies are increasingly susceptible to delayed product development turnaround times that threaten delivery schedules. These delays often occur late in development during integration when components that met the design specifications fail to achieve the req... » read more

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