tag: Cadence

Blog Review: May 1
By Jesse Allen - 01 May, 2024 - Comments: 0

Cadence's Vatsal Patel stresses the importance of having testing and training capabilities for high-bandwidth memory to prevent the entire SoC from becoming useless and points to key HBM DRAM test instructions through IEEE 1500. In a podcast, Siemens' Stephen V. Chavez chats with Anaya Vardya of American Standard Circuits about the growing significance of high density interconnect and Ultra ... » read more

Multi-Die Design Pushes Complexity To The Max
By Ann Mutschler - 29 Apr, 2024 - Comments: 1

Multi-die/multi-chiplet design has thrown a wrench into the ability to manage design complexity, driving up costs per transistor, straining market windows, and sending the entire chip industry scrambling for new tools and methodologies. For multiple decades, the entire semiconductor design ecosystem — from EDA and IP providers to foundries and equipment makers — has evolved with the assu... » read more

Chip Industry Week In Review
By The SE Staff - 26 Apr, 2024 - Comments: 0

President Biden announced four new Workforce Hubs to support the CHIPS Act and other initiatives, in Upstate New York, Michigan, Milwaukee, and Philadelphia. The White House also provided economic context and progress updates for the President’s workforce strategy. Samsung began mass production of its ninth-gen industry-first V-NAND chip. Along with one-terabit triple-level cell design, th... » read more

EDA Looks Beyond Chips
By Ed Sperling - 25 Apr, 2024 - Comments: 0

Large EDA companies are looking at huge new opportunities that reach well beyond semiconductors, combining large-scale multi-physics simulations with methodologies and tools that were developed for chips. Top EDA executives have been talking about expanding into adjacent markets for more than a decade, but the broader markets were largely closed to them. In fact, the only significant step in... » read more

Exploring The Security Framework Of RISC-V Architecture In Modern SoCs
By Anika Sunda - 25 Apr, 2024 - Comments: 0

In the rapidly evolving world of technology, system-on-chip (SoC) designs have become a cornerstone for various applications, from automotive and mobile devices to data centers. These complex systems integrate multiple processors, a multi-level cache hierarchy, and various subsystems that share memory and system resources. However, this open access to shared memory and resources introduces pote... » read more

Bridging the Gap Between Industry and Academia
By Cadence - 24 Apr, 2024 - Comments: 0

The purpose of the Cadence Academic Network is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence in the areas of verification, design, and implementation of microelectronic systems. Taking a four-pronged approach of recruiting, promoting the Cadence university software program, establishing academic p... » read more

Blog Review: April 24
By Jesse Allen - 24 Apr, 2024 - Comments: 0

Cadence's Vatsal Patel notes the factors that make high-bandwidth memory ideal for AI, such as improved bandwidth and area from vertical stacking and power reduction features like data bus inversion. Synopsys' Rob van Blommestein points to early power network analysis as a way to ensure that enough power is delivered to each transistor to mitigate potential power-related issues within the ch... » read more

Chip Industry Week In Review
By The SE Staff - 19 Apr, 2024 - Comments: 0

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Blog Review: April 17
By Jesse Allen - 17 Apr, 2024 - Comments: 0

Siemens' Sumit Vishwakarma highlights the importance of crystal oscillators to the proper functioning of many semiconductor devices and applications, from clock signals to transmission and reception of radio waves. Cadence's Jay Domadia introduces some of the new features in GDDR7, such as a semi-independent row and column command address bus and two modes of data signaling, enabling PAM3 fo... » read more

Using AI/ML To Minimize IR Drop
By Ann Mutschler - 11 Apr, 2024 - Comments: 1

IR drop is becoming a much bigger problem as technology nodes scale and more components are packed into advanced packages. This is partly a result of physics, but it's also the result of how the design flow is structured. In most cases, AI/ML can help. The underlying problem is that moving to advanced process nodes, and now 3D-ICs, is driving current densities higher, while the power envelop... » read more

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