tag: Cadence

Shrink Or Package?
By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

The Week In Review: Design
By Jesse Allen - 16 Jun, 2017 - Comments: 0

M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

Modeling On-Chip Variation At 10/7nm
By Ann Mutschler - 14 Jun, 2017 - Comments: 1

Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

Blog Review: June 14
By Jesse Allen - 14 Jun, 2017 - Comments: 0

In a video, Cadence's Tom Hackett looks at the evolving von Neumann computer architecture and the development of CCIX driven by recent cloud computing challenges. Mentor's Puneet Sinha notes it's been 17 years since the Toyota Prius went on sale worldwide, and looks ahead to the next 17 years of electric vehicles. Synopsys' Sri Deepti Pisipati gives an overview of the different topologies... » read more

ESD Guns, Transients And Testing…Oh My!
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

With the pervasiveness of power management techniques like clock gating and power gating, transient power is on the rise, accompanied by the requirement to closely examine a system for such phenomenon as electrostatic discharge. I was interested to recently learn more about ESD testing, some of which is done with software tools, but much is still done in the lab with prototypes of the end d... » read more

Transient Power Problems Rising
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

What Does “Low Power Optimization” Mean To You?
By Dave Pursley - 08 Jun, 2017 - Comments: 0

As I was researching some new low power capabilities, I asked this question of nearly every designer I met: “How important is low power optimization?” It turns out that it’s a pretty useless question because of course it’s important to just about everyone. After all, reducing power improves reliability and reduces design costs. And for chips destined for certain applications, such as mo... » read more

Safety Plus Security: A New Challenge
By Brian Bailey - 08 Jun, 2017 - Comments: 0

Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Hardware/Software Tipping Point
By Brian Bailey - 08 Jun, 2017 - Comments: 0

It doesn't matter if you believe [getkc id="74" comment="Moore's Law"] has ended or is just slowing down. It is becoming very clear that design in the future will be significant different than it is today. Moore's law allowed the semiconductor industry to reuse design blocks from previous designs, and these were helped along by a new technology node—even if it was a sub-optimal solution. I... » read more

Tech Talk: Neural Networks
By Ed Sperling - 08 Jun, 2017 - Comments: 0

Megha Daga, senior technical marketing manager at Cadence, talks with Semiconductor Engineering about convolutional neural networks, including the bandwidth and compute challenges associated with them. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy