tag: Cadence

Chip Architectures Becoming Much More Complex With Chiplets
By Ed Sperling and Ann Mutschler - 30 Jan, 2025 - Comments: 0

The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

Chiplets Still A Challenge With UCIe 2.0
By Brian Bailey - 30 Jan, 2025 - Comments: 0

Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires. Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable s... » read more

Design Customization Puts Heavy Burden On Verification
By Ann Mutschler - 30 Jan, 2025 - Comments: 0

Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor Engineering sat down with a panel of experts, including Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group director for verification software product management at Cad... » read more

Fast Monte Carlo Simulations For Timing Variation Analysis
By Vinod Khera - 30 Jan, 2025 - Comments: 0

Process variations and device mismatches profoundly affect the latest ultra-small geometrical processes. Complexity creates additional factors that impact device manufacturing variability, which in turn impact overall yield. Monte Carlo (MC) simulations use repeated random sampling to relate process variations to circuit performance and functionality, thus determining how they impact yield. How... » read more

Blog Review: Jan. 29
By Jesse Allen - 29 Jan, 2025 - Comments: 0

Cadence's Reela Samuel looks beyond silicon to new semiconductor materials under development and the particular applications for gallium nitride, silicon carbide, indium phosphide, glass, and diamond. Siemens' Kyle Fraunfelter and Melville Bryant find that lean approaches alone cannot address the increasingly complex sustainability challenges of semiconductor manufacturing and call for the e... » read more

Assembly Design Rules Slowly Emerge
By Bryon Moyer - 27 Jan, 2025 - Comments: 0

Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

Chip Industry Week In Review
By The SE Staff - 24 Jan, 2025 - Comments: 0

The new Trump administration was quick to put a different stamp on the tech world: President Trump rescinded a long list of Biden’s executive orders, including those aimed at AI safety and the mandate for 50% EVs by 2030. Roughly 1.3 million EVs were sold in the U.S. in 2024, up 7.3% from 2023. The new administration announced $500 billion ($100 billion initially) in private sector in... » read more

Automotive OEMs Face Multiple Technology Adoption Challenges
By Ann Mutschler - 22 Jan, 2025 - Comments: 0

Experts At The Table: The automotive ecosystem is in the midst of significant change. OEMs and tiered providers are grappling with how to deal with legacy technology while incorporating ever-increasing levels of autonomy, electrification, and software-defined vehicle concepts, just to name a few. Semiconductor Engineering sat down to discuss these and other related issues with Wayne Lyons, seni... » read more

Blog Review: Jan. 22
By Jesse Allen - 22 Jan, 2025 - Comments: 0

Cadence's David Shin provides an overview of the eUSB2V2 specification, which scales up to 4.8Gbps of data rate and provides the flexibility to configure either asymmetrical or symmetrical links depending on the intended application. Siemens EDA's Spencer Acain highlights the key role of AI in semiconductor testing, including the addition of analytical AI in DFT tools and how applying machin... » read more

Is Liquid Cooling The Future Of Your Data Center?
By Veena Parthan - 16 Jan, 2025 - Comments: 0

The data center industry is facing unprecedented challenges. With chip densities skyrocketing, high-performance computing is being pushed to its limits, all while energy costs are soaring and environmental concerns are escalating. Securing approvals for new data center facilities has become more complex, often plagued by community objections and grid supply issues. However, amidst these hurd... » read more

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