tag: Cadence

PCIe 6.0 Address Translation Services: Verification Challenges And Strategies
By Geeta Arora - 18 Jul, 2024 - Comments: 0

Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics ... » read more

IC Power Optimization Required, But More Difficult To Achieve
By Adam Kovac - 18 Jul, 2024 - Comments: 0

Power optimization is playing an increasingly vital role in chip and chip and system designs, but it's also becoming much harder to achieve as transistor density and system complexity continue to grow. This is especially evident with advanced packages, chiplets, and high-performance chips, all of which are becoming more common in complex designs. Inside data centers, racks of servers are str... » read more

Data Center Thermal Management Improves
By Karen Heyman - 18 Jul, 2024 - Comments: 0

Thermal issues are plaguing semiconductor design at every level, from chips developed with single-digit nanometer processes to 100,000-square-foot data centers. The underlying cause is too many devices or services that require increasing amounts of power, and too few opportunities for the resulting heat to dissipate. “Everybody wants to try to do more in a small volume of space,” said St... » read more

Blog Review: July 17
By Jesse Allen - 17 Jul, 2024 - Comments: 0

Cadence's Xin Mu explains the PCIe ECN Unordered IO (UIO) feature in the PCIe 6.1 specification, which defines a new wire semantic and related capabilities to enable multiple-path fabric support and helps avoid unnecessary traffic for better bandwidth and latency. Synopsys' Dana Neustadter, Gary Ruggles, and Richard Solomon highlight the latest updates in the CXL 3.1 standard, including new ... » read more

Cadence Janus NoC System IP
By Cadence - 17 Jul, 2024 - Comments: 0

The Cadence Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs. With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce ch... » read more

Easing EV Range Anxiety Through Faster Charging
By Ann Mutschler - 11 Jul, 2024 - Comments: 0

The automotive industry is developing new ways to boost the range of electric vehicles and the speed at which they are charged, overcoming buyer hesitation that has limited the total percentage of EVs to 18% of vehicles being sold.[1] Work is underway to improve how batteries are engineered and manufactured, and how they are managed while they are in use or being charged. This extends well b... » read more

Blog Review: July 10
By Jesse Allen - 10 Jul, 2024 - Comments: 0

Cadence's Paul Graykowski suggests using real number modeling to streamline digital mixed-signal verification using logic simulators and hardware emulators. Siemens' John McMillan and Microsoft's Amit Kumar introduce the basics of 3D-IC, describe the flow and data management challenges, look at the evolution of TSMC 3DBlox 1.0 and 2.0, and detail a physical verification and reliability analy... » read more

Chip Industry Week In Review
By The SE Staff - 03 Jul, 2024 - Comments: 0

Early version due to U.S. holiday. The U.S. government announced a new $504 million funding round for 12 Regional Technology and Innovation Hubs (Tech Hubs) for semiconductors, clean energy, biotechnology, AI, quantum computing, and more. Among the recipients: NY SMART I-Corridor Tech Hub (New York): $40 million for semiconductor manufacturing; Headwaters Hub (Montana): $41 million f... » read more

Navigating Chiplet-Based Automotive Electronics Design With Advanced Tools And Flows
By Reela Samuel - 02 Jul, 2024 - Comments: 0

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive secto... » read more

Thermal Challenges Multiply In Automotive, Embedded Devices
By Karen Heyman - 02 Jul, 2024 - Comments: 0

Embedding chips into stacked-die assemblies is creating thermal dissipation challenges that can reduce the reliability and lifespan of these devices, a growing problem as chipmakers begin cramming chiplets into advanced packages with thinner substrates between them. In the past, nearly all of these complex designs were used in tightly controlled environments, such as a large data center, whe... » read more

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