tag: Calypto

Signal And Power Integrity Cross Paths
By Ed Sperling - 05 Dec, 2014 - Comments: 2

Signal integrity and power integrity historically have been relatively independent issues, and engineers with expertise in one area generally operate independently of the other. But as more power domains are added to conserve energy and allow more features, as voltages are reduced to save battery life, and as dynamic power becomes more of a concern at advanced nodes, these worlds are suddenly m... » read more

Problems Lurk In SoC Boundaries
By Brian Bailey - 04 Dec, 2014 - Comments: 0

Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

Blog Review: Nov. 12
By Ed Sperling - 12 Nov, 2014 - Comments: 0

ARM's Eoin McCann provides a primer to software-defined networking, which uses a higher level of abstraction to create a centralized controller. This is a new twist on networking—with a bit of deja vu thrown in. Mentor's Matthew Ballance points to a perfect storm for verification—shrinking features, more layers and more embedded processors. He has some tips for how to deal with all of t... » read more

Memory Gating Power Optimizations
By Rob Eccles - 07 Nov, 2014 - Comments: 0

Saving power in SOCs is challenging. Often there are many memories, which collectively can consume a significant amount of power, compelling designers to make architectural choices to minimize power. These require a fair amount of study and may impact functionality and/or embedded software. Fortunately, memory gating can save power without impacting the architecture or the software. The... » read more

Another Tool In The Bag
By Ann Mutschler - 06 Nov, 2014 - Comments: 0

Clocks can account for 25% to 40% of total dynamic power consumption in a complex chip, so when looking for areas to reduce power, the clock tree network is a good place to start. Structurally, it is certainly possible to have single-bit flip flops with a clock that connects to every one of the flip flops, and the power in general is proportional to the number of buffers in the clock tree on... » read more

Making Accurate Power Estimates At RTL
By Rob Eccles - 14 Oct, 2014 - Comments: 0

It may seem counterintuitive, but an accurate estimation of power at Register Transfer Level can be made. In this blog, we will learn how it can be done. The main ingredient In order to understand RTL power estimation, let us first consider making the power estimation at gate level. At gate level we have a netlist that contains standard cell instances. These standard cells have been charact... » read more

Architecture Versus Silicon
By Ann Mutschler - 09 Oct, 2014 - Comments: 0

For many, if not most designs today, power is everything. Determining where power is being lost is critical to making sure the design is optimized. So where to begin? To this end, it is useful to go back to the fundamentals of what power is and what power consumption is, noted Paul Traynar, software architect at [getentity id="22021" comment="ANSYS/Apache"]. “Power is proportional to capac... » read more

Blog Review: Sept. 17
By Ed Sperling - 17 Sep, 2014 - Comments: 0

Ansys’ Benoit Debbaut looks at the Pitch drop experiment, which was started in 1927 (yes, that date is correct) to observe the excruciatingly slow movement of a thick liquid weighted down by gravity. Since inception, a total of nine drops have fallen. So when will the tenth drop fall? Place your bets...when you get around to it. Mentor’s Matthew Ballance highlights an interesting challe... » read more

Are We Headed For A Power Wall?
By Ann Mutschler - 11 Sep, 2014 - Comments: 0

A common theme in semiconductor design circles today are the many power reduction techniques available to engineers to bring the power down in their devices. While power gating and other techniques are effective today, it does lead to questions about how long they will continue providing a benefit. Anand Iyer, director of product marketing for [getentity id="22016" e_name="Calypto"], believe... » read more

IoT Brings Low Power To Forefront
By Brian Bailey - 11 Sep, 2014 - Comments: 0

Low power has become a primary design consideration over the past decade, driven by consumer portable devices packing in greater amounts of processing power and sophisticated communications, while at the same time providing extended battery life even though developments in battery technology have advanced little in the same timeframe. But the [getkc id="76" comment="Internet of Things"] (IoT) w... » read more

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