tag: capacitance

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 06 Sep, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

Building Faster Chips
By Ed Sperling - 21 Jul, 2016 - Comments: 5

By Ed Sperling and Jeff Dorsch An explosion in IoT sensor data, the onset of deep learning and AI, and the commercial rollout of augmented and virtual reality are driving a renewed interest in performance as the key metric for semiconductor design. Throughout the past decade in which mobility/smartphone dominated chip design, power replaced performance as the top driver. Processors ha... » read more

RC Delay: Bottleneck To Scaling
By Rajkumar Jakkaraju - 24 May, 2016 - Comments: 1

R = resistance — the difficulty an electrical current has in passing through a conducting material. C = capacitance — the degree to which an insulating material holds a charge. RC delay = the delay in signal speed through the circuit wiring as a result of these two effects. RC delay is important because it can become a significant obstacle to continued downward scaling of logic and... » read more

New System Requirements Demand a Creatively Choreographed Ecosystem
By Jim Feldhan - 17 Sep, 2015 - Comments: 0

In the past, integrated circuits, packages and boards were all designed independently, and yet in most cases still managed to fit together with very few functional or technical problems. However, recent advances in chip performance have changed this process dramatically. New designs, processes and materials already have been seen in packaging as high-performance semiconductor chips need to c... » read more

Tech Talk: 14nm
By Ed Sperling - 21 May, 2015 - Comments: 0

Tamer Ragheb, digital design methodology technical lead at GlobalFoundries about what's changed with 14nm finFETs, including coloring with double patterning, new corners, Miller Effects, timing issues and variability. [youtube vid=Yk6jSKCtsjU] » read more

MEMS Capacitance Extraction With Calibre xACT-3D Software
By Mentor, a Siemens Business - 14 Jan, 2015 - Comments: 0

The growing use of MEM's in today's complex products requires new approaches to capacitance calculation to ensure companies can meet their time-to-market targets while producing products that meet performance and reliability expectations. Freescale Semiconductor and Mentor Graphics collaborated to demonstrate that Calibre xACT-3D software provides a robust method for extracting node-to-node cap... » read more

Supporting LP In New Process Nodes
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 26 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts o... » read more

Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy