tag: CCIX

Pushing DRAM’s Limits
By Kevin Fogarty - 14 Dec, 2017 - Comments: 1

If humans ever do create a genuinely self-aware artificial intelligence, it may well exhibit the frustration of waiting for data arrive. The access bandwidth of DRAM-based computer memory has improved by a factor of 20x over the past two decades. Capacity increased 128x during the same period. But latency improved only 1.3x, according to Kevin Chang, a researcher at Carnegie Mellon Universit... » read more

Blog Review: Nov. 29
By Ed Sperling - 29 Nov, 2017 - Comments: 0

ANSYS' Robert Harwood offers a reminder that autonomous and assisted driving technology are still very much works in progress, and flawed ones at that. It will take an estimated 5 billion to 10 billion road miles to effectively train self-driving algorithms. So far, Google has logged about 3.5 million miles. Along the same lines, Mentor's Paul Johnston takes a look at the electric car market... » read more

Targeting And Tailoring eFPGAs
By Ed Sperling - 17 Oct, 2017 - Comments: 0

Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to discuss what's changing in the embedded FPGA world, why new levels of customization are so important, and difficulty levels for implementing embedded programmability. What follows are excerpts of that discussion. SE: There are numerous ways you can go about creating a chip these days, but many of the prot... » read more

The Week In Review: Design
By Jesse Allen - 15 Sep, 2017 - Comments: 0

Tools Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and determines the optimal formal algorithm. According to the company, the Conformal Smart Logic Equivalence Checker provides an average of 4X runtime improvement with the same resources over the pr... » read more

CCIX – What And Why?
By Richard Solomon - 14 Sep, 2017 - Comments: 0

There are two significant issues with today’s I/O interconnects: high speed storage and networking applications need more bandwidth than currently available technologies provide, and co-processing/acceleration functions need cache coherency for faster access to memory in heterogeneous multi-processor systems. These requirements are driving the development of a new specification called Cache C... » read more

The Limits Of IP Reuse
By Ed Sperling - 07 Sep, 2017 - Comments: 0

The basic business proposition for third-party IP is that it's cheaper, faster, and less problematic to buy rather than build. But things haven't exactly worked out according to plan, either for companies that license IP or those that develop it. For [getkc id="43" kc_name="IP"] licensees, just keeping track of an endless series of updates is becoming unwieldy. Complex designs often include ... » read more

CCIX Enables Machine Learning
By Brian Bailey - 31 Jul, 2017 - Comments: 5

It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

Architecture First, Node Second
By Ed Sperling - 15 Jun, 2017 - Comments: 0

What a difference a node makes. A couple of rather important changes have occurred in the move from 16/14 to 10/7nm (aside from more confusing naming conventions). First, companies that require more transistors—processor companies such as [getentity id="22846" e_name="Intel"], AMD, [getentity id="22306" comment="IBM"] and [getentity id="22676" e_name="Qualcomm"]—have come to grips with t... » read more

The Week In Review: Design
By Jesse Allen - 09 Jun, 2017 - Comments: 1

Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

Moore’s Law: Toward SW-Defined Hardware
By Ed Sperling - 15 May, 2017 - Comments: 2

Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy