Looking Forward To SPIE, And Beyond

By Katherine Derbyshire - 16 Feb, 2023 - Comments: 0

On the eve of this year’s SPIE Advanced Lithography + Patterning conference, I took a look at the IEEE Devices and Systems Roadmap’s lithography section. It’s especially notable for the emergence of EUV lithography, which has quickly become critical for advanced logic. High-NA tools to support still smaller dimensions are on the horizon. In the near-term, though, the key challenge is not ... » read more

The Impact Of EUV Resist Thickness On Via Patterning Uniformity

By Benjamin Vincent - 30 Mar, 2020 - Comments: 0

Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation during lithography and etch processing. Coventor personnel, in conjunction with our colleagues from ASML and imec, recently looked at the impact of Extreme Ultraviolet lithography (EU... » read more

Clean Focus, Dose And CD Metrology For CD Uniformity Improvement

By KLA - 11 Jun, 2019 - Comments: 0

Authors: Honggoo Leea, Sangjun Hana, Minhyung Honga, Seungyong Kima, Jieun Leea, DongYoung Leea, Eungryong Oha, Ahlin Choia, Nakyoon Kimb, John C. Robinsonc, Markus Mengelc, Pablo Rovirac, Sungchul Yooc, Raphael Getinc, Dongsub Choib, Sanghuck Jeonb aSK Hynix, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, 467-701, Korea bKLA-Tencor Korea, Starplaza bldg., 53 Metapolis-ro, Hwasung... » read more

Controlling Uniformity At The Edge

By Aaron Eppler - 19 Oct, 2017 - Comments: 0

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuitie... » read more

Using Advanced Statistical Analysis To Improve FinFET Transistor Performance

By Jimmy Gu - 21 Sep, 2017 - Comments: 0

Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators t... » read more

Multiple Lithography Options Still Remain in Play

By Paula Doe - 03 Aug, 2015 - Comments: 1

The throughput and uptime of EUV, and the overlay accuracy of 193nm immersion lithography, continue to steadily improve, though neither is yet ready for 10nm production, according to speakers at SEMICON West. Mike Lercel, ASML director, Product Marketing, reported several EUV tool sites achieved 70 percent uptime for more than a week, and one customer site had done so for more than four ... » read more

Knowledge Centers
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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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