tag: Chalmers University of Technology

Research Bits: Feb. 10
By Jesse Allen - 10 Feb, 2025 - Comments: 0

Speeding up 3D NAND etch Researchers from Lam Research, the University of Colorado Boulder, and Princeton Plasma Physics Laboratory (PPPL) investigated ways to speed up the cryogenic reactive ion etching process for 3D NAND by using a combined hydrogen fluoride gas to create the plasma. “Cryo etch with the hydrogen fluoride plasma showed a significant increase in the etching rate compared... » read more

Chip Industry Technical Paper Roundup: Feb. 4
By Linda Christensen - 04 Feb, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=403 /] Find all technical papers here. » read more

Ultranarrow Semiconductor WS2 Nanoribbon FETs (Chalmers)
By Technical Paper Link - 29 Jan, 2025 - Comments: 0

A new technical paper titled "Ultranarrow Semiconductor WS2 Nanoribbon Field-Effect Transistors" was published by researchers at Chalmers University of Technology. Abstract "Semiconducting transition metal dichalcogenides (TMDs) have attracted significant attention for their potential to develop high-performance, energy-efficient, and nanoscale electronic devices. Despite notable advancem... » read more

Chip Industry Technical Paper Roundup: Jan. 28
By Linda Christensen - 28 Jan, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=400 /] Find all technical papers here. » read more

Electronic and Transport Properties of Six TMD Heterostructures
By Technical Paper Link - 24 Jan, 2025 - Comments: 0

A new technical paper titled "Computational Assessment of I–V Curves and Tunability of 2D Semiconductor van der Waals Heterostructures" was published by researchers at Chalmers University of Technology. Abstract "Two-dimensional (2D) transition metal dichalcogenides (TMDs) have received significant interest for use in tunnel field-effect transistors (TFETs) due to their ultrathin layers... » read more

Chip Industry Technical Paper Roundup: August 20
By Linda Christensen - 20 Aug, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=252 /] More ReadingTechnical Paper Library home » read more

Freeing Up Near-Memory Capacity For Cache Using Compression Techniques In A Flat Hybrid-Memory Architecture
By Technical Paper Link - 13 Aug, 2024 - Comments: 0

A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies. Abstract: "Hybrid memories, especially combining a first-tier near memory using High-Bandwidth Memory (HBM) and a second-tier far memory using DRAM, can realize a large and low cost, high-bandwi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Jun, 2023 - Comments: 0

AMD plans to spend $135 million in Ireland over four years to boost its adaptive computing segment, formerly Xilinx. The investment will fund R&D projects for next generation AI, data center, networking, and 6G communications infrastructure. The company will also add up to 290 engineering and research positions. Argonne National Laboratory installed the final blade of its Aurora supercom... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 09 Jun, 2023 - Comments: 0

The European Union’s Chips Act Commission has approved €8.1 billion ($8.73 billion) in funding for an Important Project of Common European Interest (IPCEI). As part of this IPCEI, 56 companies, including small and medium-sized enterprises (‘SMEs') and start-ups, will undertake 68 projects in research, innovation, and deployment of microelectronics and communication technologies across th... » read more

Chip Industry’s Technical Paper Roundup: May 2
By Linda Christensen - 02 May, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=95 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

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