tag: Ciena

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 04 Oct, 2019 - Comments: 0

Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 19 Jul, 2019 - Comments: 0

Products/Services Arm rolled out its Flexible Access program, which offers system-on-a-chip design teams the capability to try out the company’s semiconductor intellectual property, along with IP from Arm partners, before they commit to licensing IP and to pay only for what they use in production. The new engagement model is expected to prove useful for Internet of Things design projects and... » read more

Adding Order And Structure To Verification
By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

Foundries Expand Planar Efforts
By Mark LaPedus - 18 Jun, 2015 - Comments: 0

Competition is heating up in the leading-edge foundry business, as vendors begin to ramp up their new 16nm/14nm finFET processes. But that’s not the only action in the foundry arena. They are also expanding their efforts in the leading-edge planar market by rolling out new 28nm and 22nm processes. On one front, TSMC is offering new 28nm variants, based on bulk CMOS technology. And on an... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 13 May, 2015 - Comments: 3

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 30 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 16 Apr, 2015 - Comments: 1

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy