Experts at the table, part 3: Cost and performance differences between FD-SOI, finFETs and 28nm LP processes; predictions about FD-SOI’s longevity; what’s after 28nm.


Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator (FD-SOI) with Philippe Magarshack, group vice president for technology R&D at STMicroelectronics; Marco Brambilla, director of engineering at Synapse Design; Mike Stuber, vice president of device engineering at Silanna; Wayne Dai, chairman and CEO of VeriSilicon; Naim Ben-Hamida, senior manager of mixed signal design and test at Ciena; Kelvin Low, senior director of foundry marketing at Samsung Semiconductor; Amir Bar-Niv, senior group director of design IP marketing at Cadence; and Mike McAweeney, senior director of product solution sales at Synopsys. What follows are excerpts of that conversation. (To view part one, click here. For part two, click here.)

SE: FD-SOI was always considered more expensive than bulk silicon. What was the crossover point? Was it double patterning and finFETs? Or did it happen before that?

Low: Expensive is relative. What are you comparing it to? There’s a wrong perception that FD-SOI is expensive because of the substrate cost The substrate cost is higher, but how much you spend on a chip is also a function of skill.

Bar-Niv: It’s not the cost per wafer that’s important. It’s the cost per die.

Low: The substrate cost is about 3X. But as ST has pointed out, 28FDSOI has a reduced number of mask steps due to process simplification. So the cost goes down there. Additionally, you can get other savings because the SoC can be made smaller, and it is easier to work with. All of that translates into overall better cost. Just looking at the substrate costs is the wrong approach.

Bar-Niv: Most customers believe FD-SOI costs will be about 10% lower per die.

Low: As long as you optimize your design and execute re-use, this is very possible.

Brambilla: When we did power analysis compared to 40nm, the cost per die—not including the mask set—is significantly different. When you consider the NRE, it’s much simpler to close the timing. That’s a huge NRE savings in itself. For some class of projects, the cost of engineering is much higher than the cost of mask sets.

Ben-Hamida: With a shorter design cycle, it ends up as a lower cost. The other side is manufacturing, yield and testing. From our perspective, that’s what we focus on. What’s the shortest path and what’s the yield.

McAweeney: From our view, the transition to FD-SOI became real as soon as Samsung signed up. Before that there was a concern about supply. ST was the only supplier, and they would consume a lot of that supply themselves. A lot of customers wouldn’t commit to it until they know a company like Samsung was involved. That was a big tipping point. Another concern was the availability of IP. Fortunately for us, ST has built a broad portfolio of IP. We work with them so we license their IP. We also have our own IP.

SE: One downside for FD-SOI compared with finFETs is performance. How big of a difference is it?

Low: 14nm FinFETs were created for more performance, lower power and more scaling. There is no doubt that 14nm finFETs will allow you to have a higher performance point compared to 28nm FD-SOI. In terms of power, finFET also provides the benefit of low power. However, if you look at overall costs, 28nm FD-SOI has a lower cost point than 14nm FinFET. Depending on the end markets, many decisions are made around cost. But if your product is a high-end server which needs extreme high performance, FD-SOI may be stretched. However, one should consider Forward Body Biasing and Overdrive options for FDSOI which will gain you the additional performance.

Magarshack: FinFETs are simply not available at 28nm. You cannot compare finFETs at 16/14nm and FD-SOI at 28nm.

SE: Understood, but it’s also a question of where do you go next. Do you move to FD-SOI or continue with device shrinking?

Magarshack: People always say FD-SOI is slower, but that’s not a fair comparison, and it’s not the whole picture. 28nm is the sweet spot. Having said that, at the next node, there are things available in FD-SOI that you cannot get with finFETs. You cannot do back biasing or forward biasing. But if you are looking for ultimate performance with the CPU always on, you will get more performance using finFETs.

Brambilla: Based on the data one company has compiled for 14nm finFETs versus FD-SOI, for what they needed they thought 14nm FD-SOI would have been faster.

Magarshack: FinFET is not an easy technology to work with.

SE: What’s the yield on 28nm FD-SOI versus a regular 28nm bulk process?

Magarshack: It’s pretty close. There is no intrinsic yield difference.

Dai: That’s why the ramp has been so quick. It surprised us.

Magarshack: You have 10% fewer masks with FD-SOI compared to bulk. For one design there are 40 compared to 44.

Dai: And the yield on the back end is the same.

SE: How about the difference in cost between a 28nm FD-SOI versus 28nm low-power?

Magarshack: It is extremely comparable. The cost of the wafer is more expensive with FD-SOI than bulk. There are four fewer masks, there are lower implant levels, and there are no stressors. That compensates in process steps for the extra cost of the substrate.

SE: There is also a lot of movement backward to lower power processes on 40 and 55nm. Is FD-SOI moving in that direction, as well?

Magarshack: We have considered creating a 40nm FD-SOI process, but at this point we’ve decided to work on yield at 28nm FD-SOI. The reason is that we want to be able to re-use as much IP as possible that we have taken so much time to develop. At that point, there is no plan to push FD-SOI to a higher node.

SE: What’s the thinking about how long FD-SOI will be popular? Will it be just 28nm, or is there more life to it than that?

Ben-Hamida: If we follow the push for higher bandwidth and throughput every two years, we will always go to the next node. But will FD-SOI be able to compete for the next 10 years? Yes. There will always be a push for higher density. But from the standpoint of technology capability, it’s staying around for the long run.

Brambilla: 28nm could be a several-generations node.

Dai: Soon we will have 22nm, and 14/16nm—whatever it’s actually called. That will make it longer. It could be a good alternative below 20nm, and in time it could be better than finFETs.

SE: Does IP need to be developed just for this process?

McAweeney: All of our physical IP has to be developed specifically for the process. That’s the nature of the beast, and it can be a challenge. You have to figure out where you’re going to make your investments, and we have made those investments in partnership with ST. We’ve also made some investments to do really high-performance 28nm LP. We do think FD-SOI has legs and enough customers that it warrants the investment.

Bar-Niv: For 14/16nm, we have ported our entire IP portfolio. For this specific node, we are going more vertically. We have identified specific applications in vertical markets. For example, we don’t see a need today to design SerDes for 28nm FD-SOI. We don’t see too many applications that will use it. It’s mainly IoT applications, and those that need low power and low thermal. We are focusing on those applications, and IP needed for those markets.


chenming hu says:

Interesting discussion but the title of the article should be “28nm vs 14nm”. Designers’ choice today is technology node, not FDSOI vs FinFET. 28nm FDSOI is a compelling alternative to 28nm bulk CMOS. The manufacturing and design cost differences discussed here are basically due to 14nm vs 28nm (double patterning) not device structures. Intel said their 22nm FinFET wafer cost was 5% more than bulk CMOS wafer. FinFET, FDSOI (I prefer the name UTB-SOI 🙂 are both excellent technologies with costs comparable to bulk CMOS and superior power/speed.

BP says:

Prof Hu,
While 28UTB-SOI is a compelling technology the design enablement is none existing! As Bar-Niv stated that they will not have a SerDes design for this node as he thinks it is not needed. In our design we need that and we do not have the resources to make our own SerDes design hence we will pass on using the 28UTB-SOI no matter how compelling it may be.

Ian Dedic says:

When you compare two basically different technologies like FinFET and FDSOI it’s not a case that one is intrinsically better than the other for all applications, they both have pros and cons which make them the best choice for different applications.

FinFETs have more drive current per unit cell area, higher capacitance, steeper subthreshold slope, no Vth tuning. FDSOI has lower drive current but also lower capacitance, lower power/current density, and the ability to tune Vth up or down using back biasing.

So in more heavily loaded circuits FinFETs clock faster, have lower leakage but also higher dynamic power and power/current density. In more lightly loaded circuits — especially if parallelisation can be used — FDSOI has lower dynamic (and total) power and can run at lower voltages with higher power efficiency than FinFETs.

For circuits with a lot of “dark silicon” or low average activity where gate density and maximum clock rate are important (e.g. mobile AP, PC CPU) FinFET is the winner. For power-critical parallel circuits with high activity running all the time at high temperature (e.g. 100G networking devices) FDSOI wins because power efficiency per gate transition is better and power/current density is lower, so fewer problems with electromigration and hotspots than FinFET. FDSOI chip size may be a bit larger but this is overridden by lower power consumption. FDSOI can also win where minimum power per operation is crucial and maximum clock rate is less important (e.g. IoT).

Both are a lot better than bulk CMOS, but in different ways. Each is better than the other in some applications and worse in others.

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