tag: clock domain crossing

Design And Verification Survey Results
By Graham Bell - 27 Feb, 2014 - Comments: 1

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins. This year, I would like ... » read more

Billion-Gate Signoff
By Graham Bell - 30 Jan, 2014 - Comments: 0

At last year’s Design and Verification Conference in San Jose, Real Intent had a tutorial session on “Pre-Simulation Verification for RTL Sign-Off.” This was a start of conversation in the industry that we have seen grow through DAC 2013 in Austin, and which is getting louder each day. Verification companies are now talking about crossing the billion-gate threshold and what can be done to... » read more

SpyGlass Flow For Xilinx FPGA
By Various Writers - 04 Dec, 2013 - Comments: 0

As the cost of doing ASIC design skyrockets, FPGAs are becoming an attractive alternative for system-on-chip (SoC) types of design. Large numbers of increasingly complex designs are now done with FPGAs, making verification a major task. Besides the usual issues of width mismatch, connectivity or synthesis-simulation mismatch, there are also problems related to multiple asynchronous clock domain... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 11 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

What Do Timing Constraints Have To Do With Clock Domain Crossing?
By Ramesh Dewangan - 07 Nov, 2013 - Comments: 0

As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality timing constraints not only reduce the total effort required to achieve timing closure, but also reduce the number of iterations during that process. In the worst case, incorrect timing constraints ca... » read more

CDC Verification Of Billion-Gate SoCs
By Various Writers - 07 Nov, 2013 - Comments: 0

Driven by growing design sizes and complexities and aggressive power requirements, design and verification engineers are witnessing an explosion in the number of asynchronous clocks. Consequently, design and verification teams spend a huge amount of time verifying the correctness of asynchronous boundaries on the chip. The paper describes three methodologies to address this issue and the benefi... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 24 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

CDC Methodology For Fast-To-Slow Clocks
By Various Writers - 24 Oct, 2013 - Comments: 0

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC identifies all the data and associated control paths in a design and will ensure that the control signals passing fr... » read more

Executive Briefing: Prakash Narain
By Ed Sperling - 12 Jul, 2013 - Comments: 0

Real Intent CEO Prakash Narain talks with System-Level Design about where are the pain points in verification; different types of signoff; the impact of third-party IP, and can the tools industry keep up with the rising complexity in semiconductor design. [youtube vid=C25VMRDXGAQ] » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

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