tag: clock frequency

HW/SW Techniques To Regulate Supply Voltage And Clock Frequency Of Intermittently-Computing Devices
By Technical Paper Link - 02 Feb, 2024 - Comments: 0

A technical paper titled “Dynamic Voltage and Frequency Scaling for Intermittent Computing” was published by researchers at Politecnico di Milano, Georgia Institute of Technology, Lahore University of Management Sciences, and Uppsala University. Abstract: "We present hardware/software techniques to intelligently regulate supply voltage and clock frequency of intermittently-computing devic... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Using More Germanium In Chips for Energy Efficiency & Achievable Clock Frequencies
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Composition Dependent Electrical Transport in Si1−xGex Nanosheets with Monolithic Single-Elementary Al Contacts" was published by researchers at TU Wien (Vienna University of Technology), Johannes Kepler University, CEA-LETI, and Swiss Federal Laboratories for Materials Science and Technology. Find the technical paper here. Published September 2022. Abstrac... » read more

What’s So Important About Processor Extensibility?
By Brian Bailey - 28 May, 2020 - Comments: 1

While the ability to extend a processor is nothing new, market dynamics are forcing a growing percentage of the industry to consider it a necessary part of their product innovation. From small IoT functions to massive data centers and artificial intelligence, the need to create an optimized processing platform is often the only way to get more performance or lower power out of the silicon area ... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 23 Mar, 2016 - Comments: 0

This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical Mobile Application Processor design, we will illustrate step-by step how to optimize: Address mapping Clock frequency Quality of Service (QoS) To read more, click here. » read more

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