tag: clock gating

Are More Processor Cores Better?
By Brian Bailey - 06 Nov, 2014 - Comments: 0

Up until the early 2000s, each generation of processor was faster, used more exotic architectures, had deeper pipelines, used more transistors, ran at higher clock frequencies and consumed more power. In fact power was rising faster than performance and led to the extrapolation that within a few generations, processors would run as hot as nuclear reactors. Something had to change, and that c... » read more

Can HLS Be Trusted?
By Brian Bailey - 08 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Mike Meredith, solutions architect at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. Part 1 of the discussion looked at the changing market for HLS and the types of customers who are adopting HLS today. Divi... » read more

Clock Gating Optimization At RTL
By Various Writers - 12 Feb, 2014 - Comments: 0

In today’s semiconductor designs, lower power consumption is mandatory for mobile and hand-held applications for longer battery life and for networking or storage devices for low carbon footprint requirements. Clock power can consume as much as 60% to 70% of total chip power and is expected to increase further in the more advanced technology nodes. Hence, reducing clock power is very importan... » read more

What’s Next For Power Optimization
By Brian Bailey - 05 Dec, 2013 - Comments: 1

Today it is difficult to find a design that does not consider some kind of power optimization. Mobile needs it to preserve battery life, data centers need it to reduce operating cost, and many are finding they need it to meet tougher regulatory requirements. In a survey conducted two years ago, there was no segment of the industry that was not taking a serious look at reducing their power profi... » read more

Smarter Clock Gating
By Various Writers - 09 May, 2013 - Comments: 0

By Ghulam Nurie With the proliferation of mobile devices, power consumption and battery life have emerged as significant concerns during chip design. There are many different techniques used for power optimization, but of all the different techniques, clock gating is the most popular and widely used technique, according to a blind, anonymous survey emailed to several thousand participants worl... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

Start Early, Cover All The Bases
By Bernard Murphy - 11 Apr, 2013 - Comments: 0

Design for low power always has challenged designers and design tools. You need to have accuracy, because you are estimating implementation-centered parameters, but you need to start early, before implementation, if you are to have any hope of meaningfully reducing power. Sure, you can always play with body-bias, but that is a crude control. Real reductions after architecture always come throug... » read more

A Balancing Act
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

Clean Your Clock
By William Ruby - 14 Feb, 2013 - Comments: 0

Lowering power consumption seems to be on every designer’s mind these days. And yet when asked about applying low-power design techniques, many engineers respond, “Well, we do clock gating ... and that’s about it.” Clock gating is low-hanging fruit when it comes to low-power design. Clock gating is also well automated, as witnessed by capabilities in modern logic synthesis tools. The... » read more

Defining Reliability In Low-Power Designs
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Ann Steffora Mutschler Having a clear understanding of what reliability means for a particular low-power application can make a significant difference when it comes to communicating with engineering team members and customers. Is reliability simply a question of how long a device can run without errors? And what happens to reliability when power modeling, verification and other design tec... » read more

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