Mitigating Voltage Droop

By Aakash Jani - 13 Jun, 2023 - Comments: 0

Voltage droop, also known as IR drop, is a phenomenon that occurs when the current in the power delivery network abruptly changes due to workload fluctuations. This can lead to supply voltage drops across system-on-chips (SoCs) which can cause severe performance degradation, limit their energy efficiency, and in extreme cases can cause catastrophic timing failures. To avoid these issues, conven... » read more

Squeezing The Margins

By Barry Pangrle - 29 Mar, 2023 - Comments: 0

Back in 2016, we looked at the MediaTek Helio X20, the first Tri-Gear mobile SoC. Tri-Gear is a step beyond ARM’s big.LITTLE concept of using two different cores that have unique power and performance characteristics, by adding a third core. The main advantage to this approach is having more core choices to best run workloads at better energy efficiency and performance operating points. At... » read more

Adaptive Clocking: Minding Your P-States And C-States

By Aakash Jani - 23 Jun, 2022 - Comments: 0

Larger processor arrays are here to stay for AI and cloud applications. For example, Ampere offers a 128-core behemoth for hyperscalers (mainly Oracle), while Esperanto integrates almost 10x more cores for AI workloads. However, power management becomes increasingly important with these arrays, and system designers need to balance dynamic power with system latency. As we march year over year, t... » read more

Early Simulation Of Multi-Cycle Paths And False Paths

By Taruna Reddy - 24 Jun, 2021 - Comments: 0

Designing with synchronous clocks avoids metastability issues on clock domain crossings, but it presents its own challenges when multi-cycle and false paths are involved. A multi-cycle path (MCP) occurs when a logical function requires more than one clock cycle to produce a final, stable result. The designer must ensure that the destination register does not clock until the result is ready. Thi... » read more

Signal Connectivity Checks Are Not Just For Design-For-Test Teams

By Pawini Mahajan - 08 Jun, 2021 - Comments: 0

By Pawini Mahajan and Raja Koneru The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are challenged not only by high gate counts and the array of internally developed and third-party IP integrated into their designs: the need to achieve high-quality manu... » read more

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

By Chris Giles - 30 May, 2019 - Comments: 0

Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

How To Close Timing With An eFPGA Hosted In An SoC

By Volkan Oktem - 03 Aug, 2017 - Comments: 0

eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines the number of LUTs, memory resources, and DSP64 blocks for their Speedcore instance. A short time later, Achronix delivers the IP as... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer