What’s Next For Semis?

By Mark LaPedus - 20 Aug, 2020 - Comments: 0

It’s been a turbulent year in the semiconductor industry. 2020 was supposed to be a strong year. Then, the coronavirus outbreak hit. Suddenly, a large percentage of countries implemented various measures to mitigate the outbreak, such as stay-at-home orders as well as business and store closures. Economic turmoil and job losses soon followed, not to mention the human tragedy involved. M... » read more

Astera Labs: Purpose-Built Connectivity

By Ed Sperling - 14 Aug, 2020 - Comments: 0

Growing amounts of data are forcing companies to rethink where data is processed and when, how and where it is moved. But solutions may vary greatly from one company to the next, and from one use case or application to the next. This is forcing the adoption of a heterogenous compute architecture that combines traditional processors, such as CPUs, GPUs and FPGAs, with AI processors and smart net... » read more

The Emergence Of Hardware As A Key Enabler For The Age Of Artificial Intelligence

By Stelios Diamantidis - 13 Aug, 2020 - Comments: 0

Over the past few decades, software has been the engine of innovation for countless applications. From PCs to mobile phones, well-defined hardware platforms and instruction set architectures (ISA) have enabled many important advancements across vertical markets. The emergence of abundant-data computing is changing the software-hardware balance in a dramatic way. Diverse AI applications in fa... » read more

RISC-V Gaining Traction

By Ed Sperling - 30 Jul, 2020 - Comments: 0

Part 1: Semiconductor Engineering sat down to discuss where and why RISC-V is doing well, with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are excerpt of that ... » read more

Memory Access In AI Systems

By Ed Sperling - 27 Jul, 2020 - Comments: 0

Memory access is a key consideration in AI system design. Ron Lowman, strategic marketing manager for IP at Synopsys, talks about how memory affects overall power consumption, why partitioning of on-chip and off-chip is so critical to performance and power, and how this changes from the cloud to the edge. » read more

Challenges For A Post-Moore’s Law World

By Ed Sperling - 27 Jul, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss challenges at the edge, the impact of open-source, and how to attract new talent, with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The con... » read more

EDA In The Cloud — Why Now?

By Mentor, a Siemens Business - 24 Jun, 2020 - Comments: 0

What is the value of cloud computing to my company? Learn how the cloud became a viable option for IC verification, and explore the ways your company can best use cloud resources to expand your compute options for both established nodes and leading-edge technologies. To read more, click here. » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 22 May, 2020 - Comments: 0

Edge, cloud, data center Cadence added new verification IP (VIP) for hyperscalar data centers that supports CXL – Compute Express Link, HBM3, and Ethernet 802.3ck. The VIP are part of Cadence’s Verification Suite. Cadence also released IP for 56G long-reach SerDes on TSMC’s N7 and N6 process technologies. Many Mentor, a Siemens Business, IC design tools are now certified TSMC’s N5 a... » read more

Layout Generators For Artificial Intelligence Hardware Design

By Benjamin Prautsch - 14 May, 2020 - Comments: 0

Artificial intelligence (AI) is a powerful tool that offers great convenience in many areas of life. In addition to improving Internet searches and online shopping, it enables driver assistance systems that can save lives, for example. AI in its various forms is the essential tool for such applications, and it can be expected to show a similar development as microelectronics did. Although AI... » read more

Using Big Data For Yield And Reliability

By Ed Sperling - 22 Apr, 2020 - Comments: 0

John O’Donnell, CEO of yieldHUB, talks about the importance of clean data for traceability, yield improvement and device reliability, where and how it gets cleaned, and why that needs to be accompanied by domain expertise. » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

What’s Next For Semis?

Astera Labs: Purpose-Built Connectivity

The Emergence Of Hardware As A Key Enabler For The Age Of Artificial Intelligence

RISC-V Gaining Traction

Memory Access In AI Systems

Challenges For A Post-Moore’s Law World

EDA In The Cloud — Why Now?

Week In Review: Auto, Security, Pervasive Computing

Layout Generators For Artificial Intelligence Hardware Design

Using Big Data For Yield And Reliability

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design