A New Co-Simulation Approach for Tolerance Analysis on Vehicle Propulsion Subsystem


An increasing demand for reducing cost and time effort of the design process via improved CAE (ComputerAided Engineer) tools and methods has characterized the automotive industry over the past two decades. One of the main challenges involves the effective simulation of a vehicle’s propulsion system dealing with different physical domains: several examples have been proposed in the literature ... » read more

Inside UVM, Take Three


The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Software Driven Test Of FPGA Prototype


Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. At the same time, these designs are not purely hardware, but these days incorporate a significa... » read more