Chip Industry Technical Paper Roundup: Feb. 4


New technical papers recently added to Semiconductor Engineering’s library: [table id=403 /] Find all technical papers here. » read more

Topology And Connection Architecture Of CXL Pooling Systems (Microsoft, Columbia)


A new technical paper titled "Octopus: Scalable Low-Cost CXL Memory Pooling" was published by researchers at University of Washington, Microsoft Azure and Columbia University. Abstract "Compute Express Link (CXL) is widely-supported interconnect standard that promises to enable memory disaggregation in data centers. CXL allows for memory pooling, which can be used to create a shared memory ... » read more

Research Bits: Jan. 7


Deep UV microLED for maskless lithography Researchers from the Hong Kong University of Science and Technology, Southern University of Science and Technology, and the Suzhou Institute of Nanotechnology developed an aluminum gallium nitride deep-ultraviolet microLED display array for maskless lithography.  They also built a maskless lithography prototype platform. "The team achieved key brea... » read more

Chip Industry Technical Paper Roundup: July 16


New technical papers recently added to Semiconductor Engineering’s library. [table id=244 /] More ReadingTechnical Paper Library home   » read more

On-Chip Communication For Programmable Accelerators In Heterogeneous SoCs (Columbia, IBM)


A technical paper titled “Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures” was published by researchers at Columbia University and IBM Thomas J. Watson Research Center. Abstract: "We present several enhancements to the open-source ESP platform to support flexible and efficient on-chip communication for programmable accelerators in het... » read more

Chip Industry Week In Review


JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

Research Bits: April 8


Annealing processor Researchers from the Tokyo University of Science designed a scalable, fully-coupled annealing processor with 4096 spins on a single board with 36 CMOS chips, with parallelized capabilities for accelerated solving of combinatorial optimization problems. "We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing prepro... » read more

Research Bits: Feb. 19


DNA assembly of 3D nanomaterials Scientists from Brookhaven National Laboratory, Columbia University, and Stony Brook University developed a method that uses DNA to instruct molecules to organize themselves into targeted 3D patterns and produce a wide variety of designed metallic and semiconductor 3D nanostructures. “We have been using DNA to program nanoscale materials for more than a de... » read more

Chip Industry Technical Paper Roundup: Feb. 19


New technical papers added to Semiconductor Engineering’s library this week. [table id=199 /] More ReadingTechnical Paper Library home » read more

New Metasurface Architecture To Deliver Ultrafast Information Processing And Versatile Terahertz Sources


A technical paper titled “Light-driven nanoscale vectorial currents” was published by researchers at Los Alamos National Laboratory, Menlo Systems, University of California Davis, Columbia University, Sandia National Laboratories, and Intellectual Ventures. Abstract: "Controlled charge flows are fundamental to many areas of science and technology, serving as carriers of energy and informa... » read more

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