tag: constraints

An Incremental Approach To Reusing Automated Tests From IPs To SoCs
By Matthew Ballance - 09 Nov, 2017 - Comments: 0

Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. A promising effort toward this end is that both commercial and in-house tools have been developed to improve the productivity and efficiency of verification at the block, subsystem, and system levels. These tools raise the level of abstraction, increase test-gen... » read more

Portable Stimulus Status Report
By Brian Bailey - 24 Aug, 2017 - Comments: 0

The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

And The Winners Are… 10 Formal Solutions To Einstein’s Riddle
By Sergio Marchese - 27 Jul, 2017 - Comments: 5

A few months back, OneSpin asked engineers to solve the classic Einstein’s Riddle using a formal tool. The challenge became hugely popular, and we received many outstanding solutions. To check out the riddle itself and the top 10 solutions created by leading engineers, click here. In this blog, we take another look at the riddle, review the best solutions and announce the winners. We ha... » read more

The Early Bird Catches The Bug Using Formal
By Dave Kelf - 28 Apr, 2016 - Comments: 0

It has been suggested that formal might replace simulation, at least in some parts of the design flow. Not likely! The question is, how can formal be layered on top of simulation flows to improve coverage and schedule? The way formal is being used at the larger semiconductor companies is evolving. In many of these companies a small team of hardcore formal experts are employed across differen... » read more

Two Constraints-Based Techniques To Address Power-Related Challenges In SoC Design
By Christine Young - 10 Sep, 2015 - Comments: 0

Power scheduling, power integrity targets, voltage drop—these are just a few of the power-related challenges you’re no doubt managing in your SoC designs. There aren’t any easy answers, but there are some emerging—and promising—techniques. Two such techniques, according to University of Toronto Professor Farid Najm, are constraints generation and constraints-based verification. “... » read more

Correct-By-Design Methodology Requires Carefully Defined Constraints
By John McMillan - 14 May, 2015 - Comments: 0

Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions. The most important constraints are defined by the design requirements of differential pairs, BGAs, low voltage devices, and high-speed parallel interfaces. The cost of rework skyrockets the fu... » read more

Constraints Ubiquity: Impact On Managing Design Closure?
By Mark Baker - 10 Jul, 2014 - Comments: 0

By Mark Baker and Ravindra Aneja Maintaining completeness, correctness and consistency of design constraints is a challenge that is pervasive in the design flow. Multiple transformations, or touch points (as illustrated in the diagram below), exist during the design implementation stages. Additionally, there are parallel stages involving IP development and handoff resulting in SoC integration ... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

Hierarchy And Pain Management
By Bernard Murphy - 10 Jun, 2013 - Comments: 0

By Bernard Murphy Hierarchy is unavoidable for any large design. It partitions development and verification complexity into digestible chunks. It enables parallel development on different parts of a system. It promotes reuse. And it provides a graceful method to partition for implementation. And yet, there are times when hierarchy gets in the way. The biggest drawback with hierarchy is that... » read more

Constraints Management
By Various Writers - 27 May, 2010 - Comments: 0

As the complexity of designs has scaled, the need to provide accurate physical constraints like timing, area, power and port locations has become increasingly important. Of these, timing constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the t... » read more

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