tag: CTE

Fine-Line RDL Structure Analysis of Fan-Out Chip-on-Substrate Platform
By ASE - 17 Apr, 2025 - Comments: 0

Abstract: "The demand for high bandwidth memory (HBM) has driven the need for advanced packaging solutions, particularly those involving fan-out layers to interconnect wafers within packages. To meet the high-bandwidth requirements of the Fan-Out Chip-on-Substrate (FOCoS) technology platform, additional layers are required. However, as the number of fanout layers increases, significant chall... » read more

Benefits And Challenges In Multi-Die Assemblies
By Ed Sperling And Laura Peters - 02 Apr, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, hybrid bonding, and new materials with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. To view part one of t... » read more

The Rise Of Thin Wafer Processing
By Laura Peters - 20 Mar, 2025 - Comments: 0

The shift from planar SoCs to 3D-ICs and advanced packages requires much thinner wafers in order to improve performance and reduce power, reducing the distance that signals need to travel and the amount of energy needed to drive them. Markets calling for ultrathin wafers are growing. The combined thickness of an HBM module with 12 DRAM dies and a base logic chip is still less than that of a ... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

FOPLP Gains Traction in Advanced Semiconductor Packaging
By Gregory Haley - 21 Nov, 2024 - Comments: 1

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

New Materials Are in High Demand
By Bryon Moyer - 19 Sep, 2024 - Comments: 0

Materials suppliers are responding to the intense pressures to improve power, performance, scaling, and cost issues, which follows a long timeline from synthesis to development and high volume manufacturing in fabs. The advances in machine learning help present a wide field of candidates, which engineers then narrow to potential use. When building standard logic semiconductor chips, the prim... » read more

Precision Patterning Options Emerge For Advanced Packaging
By Gregory Haley - 23 Jul, 2024 - Comments: 0

The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market. Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly pre... » read more

Controlling Warpage In Advanced Packages
By Laura Peters - 24 Jun, 2024 - Comments: 1

Warpage is becoming a serious concern in advanced packaging, where a heterogeneous mix of materials can cause uneven stress points during assembly and packaging, and under real workloads in the field. Warpage plays a critical role in determining whether an advanced package can be assembled successfully and meet long-term reliability targets. New advances, such as molding compounds with impro... » read more

Silicon Photonics Manufacturing Ramps Up
By Gregory Haley - 21 Mar, 2024 - Comments: 0

Circuit scaling is starting to hit a wall as the laws of physics clash with exponential increases in the volume of data, forcing chipmakers to take a much closer look at silicon photonics as a way of moving data from where it is collected to where it is processed and stored. The laws of physics are immutable. Put simply, there are limits to how fast an electron can travel through copper. The... » read more

Fan-Out Panel-Level Packaging Hurdles
By Anne Meixner - 24 Jan, 2024 - Comments: 0

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

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