Week in Review: Design, Low Power


Intel discontinued its Pathfinder for RISC-V program, according to numerous reports. The program provided a pre-silicon development environment to support IP selection and early-stage software development using Intel FPGA and simulator platforms. "Since Intel will not be providing any additional releases or bug fixes, we encourage you to promptly transition to third-party RISC-V software tools ... » read more

Week In Review: Semiconductor Manufacturing, Test


Starting in 2025, SEMICON West will move to Phoenix for a five-year annual rotation. And in 2024, it will shift dates from July to October. This year’s conference will still take place July 11 to 13 at the Moscone Center. Phoenix will first host SEMICON West on October 7-9, 2025. Thereafter, it will be held at the Moscone Center in San Francisco on the alternating years and over the long term... » read more

Week In Review: Semiconductor Manufacturing, Test


TSMC is in advanced talks with key suppliers about setting up its first potential European plant in Dresden, Germany, according to Nikkei Asia. The company held a 3nm volume production and capacity expansion ceremony at its Fab 18. TSMC also is building 3nm capacity at its Arizona site, as well as opening a global R&D Center in the Hsinchu Science Park in the second quarter of 2023, to be ... » read more

Week In Review: Design, Low Power


Top Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google's director of engineering for the Android Platform Programming Languages, noted that Android currently has more than 3 billion users and the support of more than 24,000 vendors. "We've been following RISC-V for a very ... » read more

MTJ-based Circuits Provide Low-Cost, Energy Efficient Solution For Future Hardware Implementation in SC Algorithms


A review paper titled "Review of Magnetic Tunnel Junctions for Stochastic Computing" was published by researchers at University of Minnesota Twin Cities. Funding agencies include Semiconductor Research Corporation (SRC), CAPSL, NIST, DARPA and others. Abstract: "Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as... » read more

Designing And Securing Chips For Outer Space


Design considerations for hardware used in space go far beyond radiation hardening. These devices have to perform flawlessly for years, under extreme temperature variations, and potentially banged up by space junk or other particles floating in the void over its projected lifetime. Reliability in space adds a whole different set of design considerations. For example, while it's unlikely anyo... » read more

Week In Review: Design, Low Power


Cadence unveiled a new environment to automate and accelerate the complete design closure cycle from signoff optimization through routing, static timing analysis (STA), and extraction. The Certus Closure Solution allows concurrent, full-chip optimization through a massively parallel and distributed architecture and engine shared with Cadence’s Innovus Implementation System and the Tempus Timi... » read more

10 Questions: Handel Jones


Handel Jones, CEO of International Business Strategies and author of a new book, "When AI Rules The World," sat down with Semiconductor Engineering to talk about the growth and impact of AI. What follows are excerpts of that conversation. SE: What do you see as the impact of AI on semiconductors? Jones: The fact that you have a 5G smart phone is because of AI. Steve Jobs changed the smart... » read more

Securing The Aerospace And Defense Microelectronics Supply Chain With DoD Trusted Suppliers


Since our inception 35 years ago, Synopsys has supported the U.S. defense industry. Over the last five years, we’ve increased our efforts with the government and aerospace sectors via program support at Defense Advanced Research Projects Agency (DARPA) and Intelligence Advanced Research Projects Activity (IARPA) as well as at traditional and non-traditional defense prime contractors. In 20... » read more

Week In Review: Manufacturing, Test


Some funding details are now available for the CHIPS Act in the U.S. The Biden Administration plans to spend the money in the following ways: $28 billion to establish domestic production of leading-edge logic and memory chips through grants, subsidized loans or loan guarantees; $10 billion to increase production of current-generation semiconductors and chips, and $11 billion for rese... » read more

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